Delay locked loop and integrated circuit including the same
View Patent ↗A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.
1. A delay locked loop comprising:
a first delay unit configured to output an output clock by delaying an input clock by a delay;
a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and
a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.
2. The delay locked loop of claim 1 , wherein the replica delay unit comprises:
a delay unit configured to delay the output clock by the first delay amount to output a preliminary feedback clock; and
an additional delay unit configured to output the preliminary feedback clock as the feedback clock during the first frequency operation and to delay the preliminary feedback clock by the additional delay amount and output the delayed preliminary feedback clock as the feedback clock during the second frequency operation.
3. The delay locked loop of claim 2 , wherein the additional delay unit is configured to adjust the additional delay amount to have different values depending on which one of a plurality of operational frequency ranges of the delay locked loop that the delay locked loop operates.
4. The delay locked loop of claim 2 , wherein the additional delay unit comprises:
a delay cell configured to delay the preliminary feedback clock by the additional delay amount; and
a multiplexer configured to select one of the preliminary feedback clock and an output of the delay cell based on an operational frequency that the delay locked loop operates and to output the selected one as the feedback clock.
5. The delay locked loop of claim 2 , wherein the additional delay unit comprises:
a plurality of delay cells having different additional delay amounts, respectively, wherein each of the plurality of delay cells are configured to delay the preliminary feedback clock by the respective additional delay amount; and
a multiplexer configured to select one of the preliminary feedback clock and outputs of the delay cells based on which one of a plurality of frequency ranges that the delay locked unit operates and to output the selected one as the feedback clock.
6. The delay locked loop of claim 2 , wherein the first delay unit comprises a plurality of delay cells that are each configured to delay an input by a unit delay amount.
7. An integrated circuit comprising the delay locked loop of claim 1 and further comprising:
a clock path coupled in series with the first delay unit of the delayed locked loop; and
an operation frequency detection unit to detect an operational frequency of the delayed locked loop,
wherein the clock path is configured to delay an input of the clock path by a delay equal to a first delay during the first high frequency operation and a sum of the first delay and the additional delay amount during the second frequency operation, and
the first delay of the clock path is reflected in the first delay amount of the replica delay unit of the delayed locked loop.
8. The integrated circuit of claim 7 , wherein an output of the clock path is received as an input of the first delay unit.
9. An integrated circuit, comprising:
a first clock path configured to output an input clock;
a first delay unit configured to output an output clock by delaying the input clock by a delay;
a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount during a first operational frequency of the integrated circuit and an additional delay amount during a second operational frequency of the integrated circuit, wherein the second operational frequency is lower than the first operational frequency;
a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock; and
a second clock path configured to transfer the output clock as a target clock used in a target circuit of the integrated circuit,
wherein the first and second clock paths are configured to increase a sum of delays of the first and second clock paths by the additional delay amount during the second frequency operation.
10. The integrated circuit of claim 9 , wherein the first delay amount is generated by modeling a sum of the delays in the first clock path and the second clock path.
11. The integrated circuit of claim 9 , further comprising:
an operational frequency detection unit configured to generate a control signal by detecting a range of an operational frequency of the integrated circuit.
12. The integrated circuit of claim 11 , wherein the replica delay unit comprises:
a delay unit configured to delay the output clock by the first delay amount to output a preliminary feedback clock; and
an additional delay unit configured to output the preliminary feedback clock as the feedback clock during the first frequency operation and to delay the preliminary block by the additional delay amount and output the delayed preliminary feedback clock as the feedback clock during the second frequency operation in response to the control signal.
13. The integrated circuit of claim 11 , wherein the first clock path comprises:
a first delay path configured to delay an input of the first delay path by the by a delay reflected in the first delay amount to output a preliminary input clock; and
an additional delay path configured to delay the preliminary input clock in response to the control signal and to output the delayed preliminary input clock as the input clock.
14. The integrated circuit of claim 13 , wherein the additional delay path comprises:
a delay cell configured to delay the preliminary input clock by the additional delay amount; and
a multiplexer configured to select one of the preliminary input clock and an output of the delay cell in response to the control signal, and to output the selected one as the input clock.
15. The integrated circuit of claim 13 , wherein the additional delay path comprises:
a plurality of delay cells having different additional delay amounts, respectively, in delaying the preliminary input clock; and
a multiplexer configured to select one of the preliminary input clock and outputs of the delay cells in response to the control signal, and to output the selected one as the input clock.
16. The integrated circuit of claim 11 , wherein the second clock path comprises:
a first delay path configured to delay the output clock by a delay reflected in the first delay amount in outputting a preliminary target clock; and
an additional delay path configured to delay the preliminary target clock in response to the control signal and to output the target clock.
17. The integrated circuit of claim 16 , wherein the additional delay path is further configured to output the preliminary target clock as the target clock during the first frequency operation and output the target clock by delaying the preliminary target clock by the additional delay amount during the second frequency operation.
18. The integrated circuit of claim 16 , wherein the additional delay path comprises:
a delay cell configured to delay the preliminary target clock by the additional delay amount; and
a multiplexer configured to select one of the preliminary target clock and an output of the delay cell in response to the control signal and to output the selected one as the target clock.
19. The integrated circuit of claim 16 , wherein the additional delay path comprises:
a plurality of delay cells for delaying the preliminary target clock by different delay amounts, respectively; and
a multiplexer configured to select one of the preliminary target clock and outputs of the delay cells in response to the control signal and to output the selected one as the target clock.
20. The integrated circuit of claim 9 , wherein the delay unit comprises a plurality of delay cells that are each configured to delay an input by a unit delay amount.