Block decoder of semiconductor memory device
View Patent ↗A block decoder of a semiconductor memory device includes a control signal generation circuit configured to output a control signal in response to a first address mixing signal, a second address mixing signal, and an enable period signal and a block selection signal generation circuit configured to generate a block selection signal for selecting a memory block in response to the control signal.
1. A block decoder of a semiconductor memory device, comprising:
a control signal generation circuit configured to output a control signal in response to a first address mixing signal, a second address mixing signal, and an enable period signal; and
a block selection signal generation circuit configured to generate a block selection signal for selecting a memory block in response to the control signal.
2. The block decoder of claim 1 , wherein:
the first address mixing signal is activated in a high level when at least any one of a first address signal and a second address signal is activated in a high level, and
the second address mixing signal is activated in a high level when at least any one of a third address signal and a fourth address signal is activated in a high level.
3. The block decoder of claim 2 , wherein the enable period signal comprise:
a first enable period signal activated in a period in which the first address signal and the third address signal are activated; and
a second enable period signal activated in a period in which the second address signal and the fourth address signal are activated.
4. The block decoder of claim 3 , wherein the control signal generation circuit comprises:
a first signal generator configured to generate a first signal in response to the first address mixing signal, the second address mixing signal, and the first enable period signal;
a second signal generator configured to generate a second signal in response to the first address mixing signal, the second address mixing signal, and the second enable period signal; and
a control signal output unit configured to generate the control signal in response to the first signal and the second signal.
5. The block decoder of claim 1 , wherein the block signal generation circuit comprises a depletion high voltage NMOS transistor, a high voltage PMOS transistor, and an NMOS transistor which are coupled in series between a ground voltage node and a voltage supply node for supplying a high voltage.
6. The block decoder of claim 5 , wherein:
The depletion high voltage NMOS transistor configured to supply the high voltage to the high voltage PMOS transistor in response to the control signal,
the high voltage PMOS transistor configured to raise an output node of the block selection signal generation circuit to a voltage level of the high voltage in response to the control signal, and
the NMOS transistor configured to drop the output node of the block selection signal generation circuit to a ground voltage level in response to the control signal.
7. A block decoder of a semiconductor memory device, comprising:
a first address activation signal generator configured to generate a first address activation signal in response to a first address mixing signal and a second address mixing signal;
a second address activation signal generator configured to generate a second address activation signal in response to the first address mixing signal and a second address mixing signal;
a control signal generator configured to generate a control signal in response to the first address activation signal and the second address activation signal; and
a block selection signal generator configured to generate a block selection signal in response to the control signal.
8. The block decoder of claim 7 , further comprising a reset unit configured to reset the first address activation signal to a low level in response to an enable signal.
9. The block decoder of claim 7 , wherein:
the first address mixing signal is activated in a high level when at least any one of a first address signal and a second address signal is activated in a high level, and
the second address mixing signal is activated in a high level when at least any one of a third address signal and a fourth address signal is activated in a high level.
10. The block decoder of claim 9 , wherein the first address activation signal generator is configured to generate the first address activation signal in response to the first address mixing signal, the second address mixing signal, and a first enable period signal.
11. The block decoder of claim 9 , wherein the second address activation signal generator is configured to generate the second address activation signal in response to the first address mixing signal, the second address mixing signal, and a second enable period signal.
12. The block decoder of claim 10 , wherein the first enable period signal is activated in a period in which the first address signal and the third address signal are activated.
13. The block decoder of claim 11 , wherein the second enable period signal is activated in a period in which the second address signal and the fourth address signal are activated.
14. The block decoder of claim 10 , wherein the first address activation signal generator comprises:
a logic gate configured to generate an output signal in response to the first address mixing signal and the second address mixing signal;
a transistor configured to transmit the output signal of the logic gate in response to the first enable period signal; and
a latch configured to invert the output signal transmitted by the transistor and output an inverted signal as the first address activation signal.
15. The block decoder of claim 7 , wherein the block selection signal generator comprises a depletion high voltage NMOS transistor, a high voltage PMOS transistor, and an NMOS transistor which are coupled in series between a ground voltage node and a voltage supply node for supplying a high voltage.
16. The block decoder of claim 15 , wherein:
the depletion high voltage NMOS transistor configured to supply the high voltage to the high voltage PMOS transistor in response to the control signal,
the high voltage PMOS transistor configured to raise an output node of the block selection signal generation circuit to a voltage level of the high voltage in response to the control signal, and
the NMOS transistor configured to drop the output node of the block selection signal generation circuit to a ground voltage level in response to the control signal.