Semiconductor device with MIM capacitor and method for manufacturing the same
View Patent ↗A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.
1. A semiconductor device, comprising:
a lower electrode on a substrate;
a dielectric layer on the lower electrode, the dielectric layer comprising a first dielectric region and a second dielectric region;
an upper electrode on the second dielectric region;
a hardmask on the upper electrode, the hardmask comprising one or more substances selected from the group consisting of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), silicon-on-glass (SOG), field oxide (FOX), tetraethyl orthosilicate (TEOS), plasma TEOS (PE-TEOS), high density plasma oxide, silicon nitride (SiN), and silicon oxynitride (SiON);
a spacer at a side surface of the hardmask and the upper electrode and over the first dielectric region; and
a buffer insulation layer on the hardmask and the spacer.
2. The semiconductor device of claim 1 , wherein the dielectric layer comprises high-k HfO 2 /Al 2 O 3 film stacks.
3. The semiconductor device of claim 1 , wherein the hardmask and the upper electrode have a same shape.
4. The semiconductor device of claim 1 , wherein the spacer isolates the side surface of the hardmask and the upper electrode.
5. The semiconductor device of claim 1 , wherein the second dielectric region separates the lower electrode from the upper electrode.
6. The semiconductor device of claim 1 , wherein a length of the lower electrode is greater than a length of the upper electrode.
7. The semiconductor device of claim 6 , wherein:
the lower electrode comprises TiN/Ti; and
the upper electrode comprises TiN.
8. The semiconductor device of claim 1 , wherein the first dielectric region extends from the second dielectric region and terminates approximately at an end of the spacer, the end of the spacer being on an opposite side of the spacer from a side of the spacer contacting the side surface of the hardmask and the upper electrode, and
wherein a thickness of the first dielectric region is less than a thickness of the second dielectric region.
9. The semiconductor device of claim 8 , wherein the end of the spacer is defined by the buffer insulation layer and the first dielectric region.
10. The semiconductor device of claim 1 , further comprising:
a curved dielectric region between the second dielectric region and the first dielectric region.
11. The semiconductor device of claim 10 , wherein the spacer is over the curved dielectric region.
12. The semiconductor device of claim 10 , wherein the first dielectric region extends from the curved dielectric region and terminates approximately at an end of the spacer, the end of the spacer being on an opposite side of the spacer from a side of the spacer contacting the side surface of the hardmask and the upper electrode,
wherein the curved dielectric region is configured to connect the first dielectric region and the second dielectric region, and
wherein a thickness of the first dielectric region is less than a thickness of the second dielectric region and the curved dielectric region.
13. The semiconductor device of claim 1 , wherein the buffer insulation layer comprises SiON.
14. A semiconductor device, comprising:
a lower electrode on a substrate;
a dielectric layer on the lower electrode, the dielectric layer comprising a first dielectric region, a second dielectric region, and a curved dielectric region between the second dielectric region and the first dielectric region;
an upper electrode on the second dielectric region;
a hardmask on the upper electrode;
a spacer at a side surface of the hardmask and the upper electrode and over the first dielectric region; and
a buffer insulation layer on the hardmask and the spacer.
15. The semiconductor device of claim 14 , wherein the spacer is over the curved dielectric region.
16. The semiconductor device of claim 14 , wherein the first dielectric region extends from the curved dielectric region and terminates approximately at an end of the spacer, the end of the spacer being on an opposite side of the spacer from a side of the spacer contacting the side surface of the hardmask and the upper electrode,
wherein the curved dielectric region is configured to connect the first dielectric region and the second dielectric region, and
wherein a thickness of the first dielectric region is less than a thickness of the second dielectric region and the curved dielectric region.