Semiconductor device and data processing system including the same
View Patent ↗A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low.
1. A semiconductor device comprising:
a first power line of high potential side and a second power line of low potential side that are power gated;
a third power line of high potential side and a fourth power line of low potential side that are not power gated; and
first to third logic circuits each including an input node to receive an input signal and an output node to output an output signal, wherein
the first logic circuit is connected to the first power line and the second power line,
the second logic circuit is connected to the first and fourth power lines or the third and second power lines,
the third logic circuit is connected to the third power line and the fourth power line,
the output node of the first logic circuit is connected to the input node of the second logic circuit, and
the output node of the second logic circuit is connected to the input node of the third logic circuit.
2. The semiconductor device as claimed in claim 1 , wherein
in a first state, an electric potential of the first power line and an electric potential of the second power line are equal to an electric potential of the third power line and an electric potential of the fourth power line, respectively, and
in a second state, the electric potential of the first power line is lower than the electric potential of the third power line, the electric potential of the second power line is higher than the electric potential of the fourth power line, and the electric potential of the first power line is higher than the electric potential of the second power line.
3. The semiconductor device as claimed in claim 2 , further comprising an off-leakage control circuit that supplies a first voltage between the first and second power lines in the first state and supplies a second voltage lower than the first voltage between the first and second power lines in the second state, wherein
the first voltage is supplied between the third and fourth power lines in both the first state and the second state,
the first logic circuit including first and second power nodes connected to the first and second power lines, respectively,
the second logic circuit including third and fourth power nodes connected to either the first and fourth power lines or the third and second power lines, respectively, and
the third logic circuit including fifth and sixth power nodes connected to the third and fourth power lines, respectively.
4. The semiconductor device as claimed in claim 3 , wherein
the output signal of the first logic circuit is fixed at a predetermined logic level in the second state, and
the output signal of the first logic circuit is changeable in the first state.
5. The semiconductor device as claimed in claim 4 , wherein
the output signal of the first logic circuit is fixed at an electric potential applied to the first power line in the second state, and
the third and fourth power nodes of the second logic circuit are connected to the first and fourth power lines, respectively.
6. The semiconductor device as claimed in claim 4 , wherein
the output signal of the first logic circuit is fixed at an electric potential applied to the second power line in the second state, and
the third and fourth power nodes of the second logic circuit are connected to the third and second power lines, respectively.
7. The semiconductor device as claimed in claim 3 , wherein threshold voltages of transistors included in the first and second logic circuits are lower than threshold voltages of transistors included in the third logic circuit.
8. The semiconductor device as claimed in claim 7 , wherein thicknesses of gate insulation films of the transistors included in the first and second logic circuits are thinner than thicknesses of gate insulation films of the transistors included in the third logic circuit.
9. The semiconductor device as claimed in claim 7 , wherein channel lengths between sources and drains of the transistors included in the first and second logic circuits are shorter than channel lengths between sources and drains of the transistors included in the third logic circuit.
10. The semiconductor device as claimed in claim 3 , wherein
the off-leakage control circuit includes a first switch circuit connected between the first and third power lines and a second switch circuit connected between the second and fourth power lines,
both the first and second switch circuits are in an electrical conductive state in the first state, and
both the first and second switch circuits are in an electrical non-conductive state in the second state.
11. The semiconductor device as claimed in claim 10 , wherein
the first switch circuit comprises an electric field effect transistor of a first conductivity type whose source is connected to the third power line and drain is connected to the first power line, and
the second switch circuit comprises an electric field effect transistor of a second conductivity type whose source is connected to the fourth power line and drain is connected to the second power line.
12. The semiconductor device as claimed in claim 10 , wherein the off-leakage control circuit includes a first step-down circuit connected between the first and third power lines and a second step-down circuit connected between the second and the fourth power lines.
13. The semiconductor device as claimed in claim 12 , wherein
the first and second step-down circuits comprise diodes,
an anode of the diode constituting the first step-down circuit is connected to the third power line and a cathode is connected to the first power line, and
an anode of the diode constituting the second step-down circuit is connected to the second power line and a cathode is connected to the fourth power line.
14. The semiconductor device as claimed in claim 10 , wherein
the off-leakage control circuit further includes a first regulator circuit that supplies a first potential to the first power line in the second state and a second regulator circuit that supplies a second potential to the second power line in the second state,
the first regulator circuit controls the first potential based on a predetermined electric potential applied to its own input node, and
the second regulator circuit controls the second potential based on a predetermined electric potential applied to its own input node.
15. The semiconductor device as claimed in claim 10 , wherein
the off-leakage control circuit further includes a first transistor switch having a source connected to the first power line, a drain connected to the third power line, and a gate supplied with a first control potential, and a second transistor switch having a source connected to the second power line, a drain connected to the fourth power line, and a gate supplied with a second control potential, and
an electric potential of the first power line and an electric potential of the second power line are controlled based on the first and second control potentials, respectively.
16. The semiconductor device as claimed in claim 15 , wherein
conductivity types of an electric field effect transistor constituting the first switch circuit and an electric field effect transistor constituting the first transistor switch are mutually opposite, and
conductivity types of an electric field effect transistor constituting the second switch circuit and an electric field effect transistor constituting the second transistor switch are mutually opposite.
17. A semiconductor device comprising:
first and third power lines supplied with an electric potential showing a logical high level, respectively;
second and fourth power lines supplied with an electric potential showing a logical low level, respectively;
a first off-leakage control circuit that supplies the first power line with an electric potential that is same as an electric potential of the third power line in a first state, and supplies the first power line with an electric potential that is lower than the electric potential of the third power line in a second state;
a second off-leakage control circuit that supplies the second power line with an electric potential that is same as an electric potential of the fourth power line in the first state, and supplies the second power line with an electric potential that is higher than the electric potential of the fourth power line in the second state;
a first circuit block including a power node on a high potential side connected to the first power line and a power node on a low potential side connected to the second power line;
a second circuit block including a power node on a high potential side is connected to the third power line and a power node on a low potential side connected to the fourth power line; and
a logic circuit including an input connected to an output node of the first circuit block and an output node connected to an input node of the second circuit block, wherein
the logic circuit, in the first state, dynamically supplies the input node of the second circuit block with a signal of the logical high level via the third power line or a signal of the logical low level via the second power line, or, dynamically supplies the input node of the second circuit block with a signal of the logical high level via the first power line or a signal of the logical low level via the fourth power line, based on an output signal output from the output node of the first circuit block, and
the logic circuit, in the second state, fixedly supplies the input node of the second circuit block with the signal of the logical high level via the third power line, or fixedly supplies to the input node of the second circuit block with the signal of the logical low level via the fourth power line based on an output signal output from the output node of the first circuit block.
18. The semiconductor device as claimed in claim 17 , wherein
the logic circuit includes first and second conductivity type transistors having gates commonly supplied with the output signal of the first circuit block, the first and second conductivity type transistors being serially connected in between the first and fourth power lines,
the output signal output from the output node of the first circuit block is fixed at the logical high level in the second state,
the first conductivity type transistor becomes electrically conducting when the output signal output from the output node of the logic circuit is in the logical high level, and
the second conductivity type transistor becomes electrically conducting when the output signal output from the output node of the logic circuit is in the logical low level.
19. The semiconductor device as claimed in claim 17 , wherein
the logic circuit includes first and second conductivity type transistors having gates commonly supplied with the output signal of the first circuit block, the first and second conductivity type transistors being serially connected in between the third and second power lines,
the output signal output from the output node of the first circuit block is fixed at the logical low level in the second state,
the first conductivity type transistor becomes electrically conducting when the output signal output from the output node of the logic circuit is in the logical high level, and
the second conductivity type transistor becomes electrically conducting when the output signal output from the output node of the logic circuit is in the logical low level.
20. The semiconductor device as claimed in claim 17 , wherein a threshold voltage of a transistor included in the first circuit block is lower than a threshold voltage of a transistor included in the second circuit block.
21. The semiconductor device as claimed in claim 20 , wherein a threshold voltage of a transistor included in the logic circuit is lower than the threshold voltage of the transistor included in the second circuit block.
22. The semiconductor device as claimed in claim 17 , wherein
the first off-leakage control circuit includes a first switch circuit connected between the first and third power lines,
the second off-leakage control circuit includes a second switch circuit connected between the second and fourth power lines,
both the first and second switch circuits are in an electrical conductive state in the first state, and
both the first and second switch circuits are in an electrical non-conductive state in the second state.
23. The semiconductor device as claimed in claim 22 , wherein
the first off-leakage control circuit further includes a first regulator circuit that supplies the first power line with a first potential in the second state,
the second off-leakage control circuit further includes a second regulator circuit that supplies the second power line with a second potential in the second state,
the first regulator circuit controls the first potential based on a predetermined electric potential applied to its own input node, and
the second regulator circuit controls the second potential based on a predetermined electric potential applied to its own input node.
24. The semiconductor device as claimed in claim 22 , wherein
the first off-leakage control circuit further includes a first transistor switch having a source connected to the first power line, a drain connected to the third power line, and a gate supplied with a first control potential,
the second off-leakage control circuit further includes a second transistor switch having a source connected to the second power line, a drain connected to the fourth power line, and a gate supplied with a second control potential, and
an electric potential of the first power line and an electric potential of the second power line are controlled based on the first and second control potentials, respectively.
25. A data processing system comprising:
a semiconductor device;
a controller that supplies a command to the semiconductor device, wherein
the semiconductor device enters in a first state or a second state based on the command,
the semiconductor device comprises:
a first power line of high potential side and a second power line of low potential side that are power gated;
a third power line of high potential side and a fourth power line of low potential side that are not power gated; and
first to third logic circuits each including an input node to receive an input signal and an output node to output an output signal, wherein
the first logic circuit is connected to the first power line and the second power line,
the second logic circuit is connected to the first and fourth power lines or the third and second power lines,
the third logic circuit is connected to the third power line and the fourth power line,
the output node of the first logic circuit is connected to the input node of the second logic circuit,
the output node of the second logic circuit is connected to the input node of the third logic circuit,
in the first state, an electric potential of the first power line and an electric potential of the second power line are equal to an electric potential of the third power line and an electric potential of the fourth power line, respectively, and
in the second state, the electric potential of the first power line is lower than the electric potential of the third power line, the electric potential of the second power line is higher than the electric potential of the fourth power line, and the electric potential of the first power line is higher than the electric potential of the second power line.
26. A data processing system comprising:
a semiconductor device; and
a controller that supplies a command to the semiconductor device, wherein
the semiconductor device enters in a first state or a second state based on the command,
the semiconductor device comprises:
first and third power lines supplied with an electric potential showing a logical high level, respectively;
second and fourth power lines supplied with an electric potential showing a logical low level, respectively;
a first off-leakage control circuit that supplies the first power line with an electric potential that is same as an electric potential of the third power line in the first state, and supplies the first power line with an electric potential that is lower than the electric potential of the third power line in the second state;
a second off-leakage control circuit that supplies the second power line with an electric potential that is same as an electric potential of the fourth power line in the first state, and supplies the second power line with an electric potential that is higher than the electric potential of the fourth power line in the second state;
a first circuit block including a power node on a high potential side connected to the first power line and a power node on a low potential side connected to the second power line;
a second circuit block including a power node on a high potential side is connected to the third power line and a power node on a low potential side connected to the fourth power line; and
a logic circuit including an input connected to an output node of the first circuit block and an output node connected to an input node of the second circuit block, wherein
the logic circuit, in the first state, dynamically supplies the input node of the second circuit block with a signal of the logical high level via the third power line or a signal of the logical low level via the second power line, or, dynamically supplies the input node of the second circuit block with a signal of the logical high level via the first power line or a signal of the logical low level via the fourth power line, based on an output signal output from the output node of the first circuit block, and
the logic circuit, in the second state, fixedly supplies the input node of the second circuit block with the signal of the logical high level via the third power line, or fixedly supplies to the input node of the second circuit block with the signal of the logical low level via the fourth power line based on an output signal output from the output node of the first circuit block.