IP Library Granted Patent US 8,384,324
Granted Patent B2
US 8,384,324 · App. 13/010,506 · Granted Feb 26, 2013

Motor drive circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,384,324
App. No.
13/010,506
Granted
Feb 26, 2013
Kind
B2
Abstract

A motor drive circuit is configured to drive a motor based on first and second position detection signals opposite in phase to each other, the signals having a frequency corresponding to a rotational speed of the motor and indicating a rotational position of the motor. The circuit includes a first level-shift circuit, a second level-shift circuit, a timing detecting circuit, and an output circuit. The first level-shift circuit is configured to shift a level of at least either one of the first and second position detection signals so that a first period, during which a first output signal corresponding to the first position detection signal is higher in level than a second output signal corresponding to the second position detection signal, becomes longer than a second period, during which the second output signal is higher in level than the first output signal.

Claims (39)

1. A motor drive circuit configured to drive a motor based on first and second position detection signals opposite in phase to each other, the signals having a frequency corresponding to a rotational speed of the motor and indicating a rotational position of the motor, the circuit comprising:

a first level-shift circuit configured to shift a level of at least either one of the first and second position detection signals so that a period, during which a first output signal corresponding to the first position detection signal is higher in level than a second output signal corresponding to the second position detection signal, becomes longer than a period, during which the second output signal is higher in level than the first output signal;

a second level-shift circuit configured to shift a level of at least either one of the first and second position detection signals so that a period, during which a third output signal corresponding to the first position detection signal is higher in level than a fourth output signal corresponding to the second position detection signal, becomes shorter than a period, during which the fourth output signal is higher in level than the third output signal;

a timing detecting circuit configured to detect first timing at which the first and second output signals cross in level, and second timing at which the third and fourth output signals cross in level; and

an output circuit configured to output, to a drive circuit configured to drive a coil of the motor, an instruction signal for changing a drive current of the coil in a gradual manner only during a period between the first timing and the second timing, the period including a third timing at which the first and second position detection signals cross in level.

2. The motor drive circuit according to claim 1 , wherein

the timing detecting circuit includes:

a first comparison circuit configured to compare the levels between the first and second output signals, to detect the first timing; and

a second comparison circuit configured to compare the levels between the third and fourth output signals, to detect the second timing.

3. The motor drive circuit according to claim 2 , wherein

the first level-shift circuit includes:

a first transistor having a control electrode to which the first position detection signal is input;

a first resistor having one end connected to an output electrode of the first transistor;

a first bias current source connected in series to the first resistor so that the first output signal is output from the other end of the first resistor;

a second transistor having a control electrode to which the second position detection signal is input; and

a second bias current source connected in series to the second transistor so that the second output signal is output from an output electrode of the second transistor, and wherein

the second level-shift circuit includes:

a third transistor having a control electrode to which the first position detection signal is input;

a third bias current source connected in series to the third transistor so that the third output signal is output from an output electrode of the third transistor;

a fourth transistor having a control electrode to which the second position detection signal is input;

a second resistor having one end connected to an output electrode of the fourth transistor; and

a fourth bias current source connected in series to the second resistor so that the fourth output signal is output from the other end of the second resistor.

4. The motor drive circuit according to claim 1 , wherein

the first level-shift circuit includes:

a first transistor having a control electrode to which the first position detection signal is input;

a first resistor having one end connected to an output electrode of the first transistor;

a first bias current source connected in series to the first resistor so that the first output signal is output from the other end of the first resistor;

a second transistor having a control electrode to which the second position detection signal is input; and

a second bias current source connected in series to the second transistor so that the second output signal is output from an output electrode of the second transistor, and wherein

the second level-shift circuit includes:

a third transistor having a control electrode to which the first position detection signal is input;

a third bias current source connected in series to the third transistor so that the third output signal is output from an output electrode of the third transistor;

a fourth transistor having a control electrode to which the second position detection signal is input;

a second resistor having one end connected to an output electrode of the fourth transistor; and

a fourth bias current source connected in series to the second resistor so that the fourth output signal is output from the other end of the second resistor.

5. The motor drive circuit according to claim 4 , wherein

the first to fourth bias current sources generate currents of the same current value.

6. The motor drive circuit according to claim 5 , wherein

the first resistor is equal in resistance value to the second resistor.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2014
From: ON SEMICONDUCTOR TRADING SARL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033626/0753 →
CHANGE OF NAME Recorded Aug 22, 2014
From: ON SEMICONDUCTOR TRADING, LTD.
To: ON SEMICONDUCTOR TRADING SARL
Reel/Frame 033596/0245 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2011
From: NAKAHATA, MASAHIRO; IMAI, TOSHIYUKI
To: ON SEMICONDUCTOR TRADING, LTD.
Reel/Frame 026443/0462 →