Hybrid structure of multi-layer substrates and manufacture method thereof
A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.
1. A manufacture method of a hybrid structure of multi-layer substrates for connecting chip devices, the manufacture method comprising steps of:
separating a border district of at least one metal layer and the corresponding dielectric layer from adjacent metal layers and adjacent dielectric layers for each multi-layer substrate; and
connecting electric conductor in a VIA of a first metal layer of one multi-layer substrate with a separated border district of a metal layer of another multi-layer substrate to form a connection section, wherein each multi-layer substrate is flexible and the connection section is also flexible.
2. The manufacture method of claim 1 , further comprising a step of removing a border district of the dielectric layer adjacent to the chip devices to reveal a border district of the corresponding metal layer.
3. The manufacture method of claim 1 , further comprising a step of forming the multi-layer substrates on the chip devices before the separating step.
4. The manufacture method of claim 3 , further comprises a step of implementing an interface adhesion enhancing process on the chip devices during the step of forming the multi-layer substrates.
5. The manufacture method of claim 3 , wherein the step of forming the multi-layer substrates further comprises steps of:
(A) coating a dielectric layer on the surfaces of the chip devices;
(B) forming a plurality of VIAs at the dielectric layer and a metal layer on the dielectric layer;
(C) coating another dielectric layer;
(D) repeating the step (B) and the step (C) to form the multi-layer substrates.
6. The manufacture method of claim 5 , further comprising a step of implementing an interface adhesion enhancing process on rest surface of the metal layer and the corresponding dielectric layer except the border district to increase adhesion intensity on the rest surfaces before coating the another dielectric layer during the step (C).
7. The manufacture method of claim 5 , further comprising a step of implementing an interface adhesion weakening process on the border district to decrease adhesion intensity thereon before coating the another dielectric layer during the step (C).
8. The manufacture method of claim 5 , further comprising a step of providing a device wafer including the chip devices.
9. The manufacture method of claim 8 , further comprising a step of dividing the chip devices and corresponding multi-layer substrates along edges of the border districts.
10. The manufacture method of claim 9 , further comprising a step of removing parts of the device wafer without chip devices after the step of dividing the chip devices.
11. The manufacture method of claim 1 , further comprising a step of connecting the multi-layer substrates with a third substrate after the connecting step.