IP Library Granted Patent US 8,159,292
Granted Patent B2
US 8,159,292 · App. 13/032,245 · Granted Apr 17, 2012

Amplifying circuit

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Quick Facts
Patent No.
US 8,159,292
App. No.
13/032,245
Granted
Apr 17, 2012
Kind
B2
Abstract

To efficiently obtain two outputs including one at a normal level and the other at an excessive level. An input signal input to the negative input terminal of an operational amplifier ( 14 ) having a negative feedback path is amplified to output an output signal. Signal combining units ( 18, 20, 22 ) are provided for adding in a weighted manner a negative input terminal side signal obtained by combining the input signal input to the negative input terminal of the operational amplifier ( 14 ) and a feedback signal from the negative feedback path and the output signal from the operational amplifier to output a combined signal, so that two signals, namely the output signal from the operational amplifier ( 14 ) and the combined signal, are obtained.

Claims (25)

1. An amplifying circuit, comprising:

an operational amplifier having a negative feedback path, for amplifying an input signal input to a negative input terminal and outputting an output signal; and

signal combining means for adding in a weighted manner a negative input terminal side signal and the output signal output from the operational amplifier to output a combined signal, the negative input terminal side signal being obtained by adding the input signal input to the negative input terminal of the operational amplifier and a feedback signal from the negative feedback path,

wherein

two signals, namely, the output signal output from the operational amplifier and the combined signal output from the signal combining means, are obtained.

2. The amplifying circuit according to claim 1 , wherein

when the input signal has a large amplitude and the output signal from the operational amplifier is distorted with a part thereof equal to or larger than an output upper limit being cut off, the signal combining means obtains a combined signal corresponding to a waveform of the input signal.

3. The amplifying circuit according to claim 1 , wherein

the input signal is a signal from an equivalent circuit of an electret condenser microphone, the equivalent circuit being formed by a serially connected AC signal source and capacitor,

a capacitor is provided in the negative feedback path of the operational amplifier, and

the negative input terminal side signal is extracted from the negative input terminal of the operational amplifier.

4. The amplifying circuit according to claim 1 , wherein

the signal combining means includes

a first multiplying circuit for multiplying the negative input terminal side signal by a coefficient K 1 ,

a second multiplying circuit for multiplying the output signal from the operational amplifier by a coefficient K 2 , and

an adder for adding an output from the first multiplying circuit and an output from the second multiplying circuit.

5. The amplifying circuit according to claim 1 , wherein

the input signal is a signal from an equivalent circuit of an electret condenser microphone, the equivalent circuit being formed by a serially connected AC signal source and capacitor,

two capacitors are provided in the negative feedback path of the operational amplifier, and

the negative input terminal side signal is extracted from a mid-connection point between the two capacitors provided in the negative feedback path.

6. The amplifying circuit according to claim 1 , wherein

the input signal is a signal from an equivalent circuit of an electret condenser microphone, the equivalent circuit being formed by a serially connected AC signal source and capacitor,

the operational amplifier is fully differential type, and has an inverted output terminal and a non-inverted output terminal,

the inverted output terminal is connected via a capacitor to the negative input terminal, and

the non-inverted output terminal is connected via a capacitor to a positive input terminal that is grounded via a capacitor.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2014
From: ON SEMICONDUCTOR TRADING SARL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033626/0753 →
CHANGE OF NAME Recorded Aug 22, 2014
From: ON SEMICONDUCTOR TRADING, LTD.
To: ON SEMICONDUCTOR TRADING SARL
Reel/Frame 033596/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2012
From: KANAYA, MASAHITO
To: ON SEMICONDUCTOR TRADING, LTD.
Reel/Frame 027610/0188 →