Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.
1. A system comprising:
a pre-decode block to:
receive a request address associated with a memory request corresponding to memory cells in a memory system;
rearrange the request address into a first memory address according to a first definition if the request address corresponds to memory cells in a first region of the memory system; and
comparing a size of the request address to a channel depth of the region to which the request address is directed, wherein the channel depth comprises a number of bytes to be accessed from the channel before the request address moves to another channel;
rearrange the request address into a second memory address according to a second definition if the request address corresponds to memory cells in a second region of the memory system, the second definition being different from the first definition; and
a memory controller configured to receive the first or the second memory address and to execute at least a portion of the memory request in the memory system.
2. The system of claim 1 , wherein the memory system comprises a plurality of memory devices including data pins coupled to a bus to transfer data through the bus.
3. The system of claim 1 , wherein the memory devices comprise dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, and/or Flash memory devices in any combination.
4. The system of claim 1 , wherein the pre-decode block is coupled to a plurality of masters through a bus to receive memory requests from the masters.
5. The system of claim 4 , wherein a first one of the masters comprises a general processor.
6. The system of claim 4 , wherein a second one of the masters comprises a graphics processor.
7. A method comprising:
receiving a request address associated with a memory request from a master in a pre-decode block;
determining a region of a memory system to which the request address is directed;
comparing a size of the memory request to a channel depth of the region to which the request address is directed, wherein the channel depth comprises a number of bytes to be accessed from the channel before the request address moves to another channel;
rearranging digits of the request address into a first memory address according to a first definition if the request address corresponds to memory cells in a first region of the memory system; and
rearranging the digits of the request address into a second memory address according to a second definition if the request address corresponds to memory cells in a second region of the memory system, the second definition being different from the first definition.
8. The system of claim 1 , wherein each of the regions is configured with respect to a type of access that will occur in the respective region.
9. The system of claim 1 , wherein the type of access that will occur in the respective region is based on a type of data stored in the respective region.
10. The system of claim 1 , wherein each of the regions is configured based on a type of data to be stored in the respective region.
11. The system of claim 1 , further comprising at least first and second registers, wherein the first register defines the first region and the second register defines the second region.
12. The system of claim 1 , wherein the address definitions are channel address definitions.
13. The system of claim 1 , wherein the first region has a different channel depth than the second region.
14. The system of claim 1 , wherein the memory controller is configured to execute memory requests in a memory system, wherein the memory controller includes a memory map configured to divide memory cells in the memory system into a plurality of regions, wherein each of the regions has its own address definition and each region is coupled to a different channel, each channel having a different channel depth.
15. The method of claim 7 , further comprising generating sub-transactions, each sub-transaction being a portion of the memory request to be written to or read from the region.
16. The method of claim 7 , further comprising determining a depth of channels in the region of the memory system to which the request address is directed.
17. The method of claim 7 , wherein channels in the second region of the memory system comprise more bytes than channels in the first region of the memory system.
18. The method of claim 7 , further comprising executing at least a portion of the memory request in a memory controller coupled between the pre-decode block and the memory system.