Semiconductor device with void detection monitor
View Patent ↗Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a metal portion is formed on the insulating film to fill the plurality of holes. The metal portion is polished until the insulating film is exposed and a recessed portion is formed in the void detection structure. It is determined if a void exists in the element portion of the semiconductor device by determining whether or not a void is exposed at a surface of the recessed portion of the void detection structure.
1. A semiconductor device comprising:
an element portion and a void detection monitor formed on a substrate;
an insulating film formed on the substrate; and
a plurality of metal portions each extending through the insulating film, wherein the void detection monitor comprises the plurality of metal portions and has a dish-like recess portion and wherein the element portion has a flat surface.
2. The semiconductor device according to claim 1 , wherein an area occupancy of a total area viewed from the top of a plurality of metal portions in the void detection monitor to an area viewed from the top of the void detection monitor is larger than that of the total area viewed from the top of a plurality of metal portions in the element portion to the area viewed from the top of the element portion.
3. The semiconductor device according to claim 1 , wherein the insulating film comprises a plurality of holes wherein the plurality of holes are formed so that an area occupancy of a total area viewed from the top of a plurality of holes in the void detection monitor to an area viewed from the top of the void detection monitor becomes larger than that of the area viewed from the top of a plurality of holes in the element portion to the area viewed from the top of the element portion.
4. The semiconductor device according to claim 1 , wherein the insulating film comprises a plurality of holes wherein the plurality of the holes are formed so that each cross-sectional shape of a plurality of holes of the void detection monitor is the same as that of a plurality of holes of the element portion.
5. The semiconductor device according to claim 1 , wherein the insulating film comprises a plurality of holes wherein the plurality of holes are formed in a line pattern or a dotted pattern.
6. The semiconductor device according to claim 1 , wherein the insulating film includes an inter-layer insulating film, and the metal portions include a via plug.
7. The semiconductor device according to claim 1 , wherein the insulating film includes an inter-layer insulating film, and the metal portions include an interconnection layer and a via plug.
8. The semiconductor device according to claim 1 , wherein the insulating film is formed of SiO 2 , and the metal portions are formed of Cu.
9. A semiconductor device, comprising:
a substrate;
an insulating film formed on the substrate;
an element portion comprising metal formed in vias in the insulating film wherein the top surface of the element portion is planar; and
a void detection monitor comprising metal formed in vias in the insulating film, wherein the surface of the void detection monitor comprises a dish-like recess portion that facilitates the detection of voids.
10. The semiconductor device according to claim 9 wherein the element portion comprises a memory cell region and a peripheral cell region.
11. The semiconductor device according to claim 10 wherein Cu metal line patterns in the memory cell region have a Cu occupancy of less than 30 percent and Cu metal line patterns in the void detection monitor have a Cu occupancy of greater than 90 percent.
12. The semiconductor device according to claim 11 wherein the Cu metal line patterns comprise a via chain pattern.
13. The semiconductor device according to claim 11 wherein the metal line patterns in the memory cell region are dual damascene line patterns and the metal line patterns in the void detection monitor are single damascene type line patterns.