System and method for designing integrated circuits that employ adaptive voltage scaling optimization
A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit.
1. A design process system for designing a circuit, comprising:
a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which said circuit is to be constructed; and
a PVT library selector coupled to said PVT libraries database and configured to receive a selection indicating a supplemental objective for said designing said circuit and respond to said selection by selecting one of said PVT libraries from said PVT libraries database, a timing signoff tool later employing at most two corners from said one of said PVT libraries to perform a timing signoff with respect to said circuit, wherein said at most two PVT corners are realistic corners.
2. The system as recited in claim 1 wherein said PVT library selector selects:
a fast-low-nominal PVT library if said supplemental objective is a reduced power consumption,
a typical-typical-nominal PVT library if said supplemental objective is a compromise between said reduced power consumption and a reduced turn-around time, and
a slow-high-nominal PVT library if said supplemental objective is said reduced turn-around time.
3. The system as recited in claim 2 wherein said reduced power consumption is a minimum power consumption.
4. The system as recited in claim 1 wherein said PVT libraries include a selected one of R, C and RC characterizations of said devices.
5. The system as recited in claim 1 wherein:
timing is closed for setup and hold violations with respective high and low temperature reports at a fast-low-nominal/Cbest corner if said supplemental objective is a reduced power consumption;
timing is closed for setup and hold violations with maximum and minimum reports at a typical-typical-nominal/Cnom corner if said supplemental objective is a compromise between said reduced power consumption and a reduced turn-around time; and
timing is closed for setup and hold violations with respective high and low temperature reports at a slow-high-nominal/Cworst corner if said supplemental objective is said reduced turn-around time.
6. The system as recited in claim 1 wherein said timing signoff tool also employs static or dynamic adaptive voltage and scaling optimization margins to perform said timing signoff.
7. The system as recited in claim 1 wherein said circuit is an integrated circuit employing adaptive voltage and scaling optimization.
8. The design process system as recited in claim 1 wherein a primary objective for designing said circuit is to operate at a nominal operating frequency and said supplemental objective differs from said primary objective.
9. A method of designing a circuit, comprising:
receiving a selection for a supplemental objective for said designing of said circuit;
selecting a process-voltage-temperature (PVT) library from a PVT libraries database in response to said selection of said supplemental objective;
synthesizing a logical structure of said circuit;
placing constituent cells of said circuit in a layout using an appropriate cell library;
routing interconnects among said constituent cells; and
performing a timing signoff using at most two PVT corners from said PVT library, wherein said at most two PVT corners are realistic corners.
10. The method as recited in claim 9 wherein said selecting said PVT library comprises:
selecting a fast-low-nominal PVT library if said supplemental objective is a reduced power consumption,
selecting a typical-typical-nominal PVT library if said supplemental objective is a compromise between reduced power consumption and reduced turn-around time, and
selecting a slow-high-nominal PVT library if said supplemental objective is said reduced turn-around time.
11. The method as recited in claim 10 wherein said reduced power consumption is a minimum power consumption.
12. The method as recited in claim 9 wherein said PVT libraries include a selected one of R, C and RC characterizations of said devices.
13. The method as recited in claim 9 further comprising:
employing respective high and low temperature reports at a fast-low-nominal/Cbest corner to close timing for setup and hold violations in said circuit if said supplemental objective is a reduced power consumption;
employing respective maximum and minimum reports at a typical-typical-nominal/Cnom corner to close timing for setup and hold violations in said circuit if said supplemental objective is a compromise between said reduced power consumption and a reduced turn-around time; and
employing respective high and low temperature reports at a slow-high-nominal/Cworst corner to close timing for setup and hold violations in said circuit if said supplemental objective is said reduced turn-around time.
14. The method as recited in claim 9 further comprising employing static or dynamic adaptive voltage and scaling optimization margins to perform said timing signoff.
15. The method as recited in claim 9 wherein said circuit is an integrated circuit employing adaptive voltage and scaling optimization.