Frequency adjusting apparatus and DLL circuit including the same
View Patent ↗A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.
1. A DLL (Delay Locked Loop) circuit, comprising:
a frequency adjusting apparatus configured to cyclically increase or decrease the frequency of a reference clock signal, thereby generating a frequency-adjusted clock signal;
a delay apparatus coupled with the frequency adjusting apparatus, the delay apparatus configured to delay the frequency-adjusted clock signal in response to a delay control signal, thereby generating a delayed clock signal;
a delay compensating apparatus coupled with the delay apparatus, the delay compensating apparatus configured to apply a delay time, which is obtained by modeling a delay amount on an output path of the delayed clock signal, to the delayed clock signal, thereby generating a feedback clock signal;
a phase comparing apparatus coupled with the delay compensating apparatus, the phase comparing apparatus configured to compare the phase of the reference clock signal with the phase of the feedback clock signal, thereby generating a phase comparison signal; and
a delay control apparatus coupled with the phase comparing apparatus, the delay control apparatus configured to generate the delay control signal in response to the phase comparison signal, wherein
the frequency adjusting apparatus includes:
a clock signal dividing unit configured to divide the frequency of the reference clock signal to generate a divided clock signal;
a frequency control signal generating unit configured to generate a multi-bit frequency control signal, which is changed in level bit by bit, in response to the divided clock signal; and
a frequency adjusting unit configured to adjust the frequency of the reference clock signal in response to the multi-bit frequency control signal and generate the frequency-adjusted clock signal.
2. The DLL circuit of claim 1 , wherein the frequency control signal generating unit is configured to cyclically increase or decrease the number of high-level signals in the multi-bit frequency control signal in synchronization with the toggle timing of the divided clock signal.
3. The DLL circuit of claim 1 , wherein the frequency adjusting unit cyclically is configured to increase or decrease a delay time to be applied to the reference clock signal according to a cyclical change in the logical value of the frequency control signal.
4. The DLL circuit of claim 1 , further comprising a clock signal input buffer configured to buffer an external clock signal and generate the reference clock signal.
5. A DLL (Delay Locked Loop) circuit, comprising:
a frequency adjusting apparatus configured to cyclically increase or decrease the frequency of a reference clock signal, thereby generating a frequency-adjusted clock signal;
a delay apparatus coupled with the frequency adjusting apparatus, the delay apparatus configured to delay the frequency-adjusted clock signal in response to a delay control signal, thereby generating a delayed clock signal;
a delay compensating apparatus coupled with the delay apparatus, the delay compensating apparatus configured to apply a delay time, which is obtained by modeling a delay amount on an output path of the delayed clock signal, to the delayed clock signal, thereby generating a feedback clock signal;
a phase comparing apparatus coupled with the delay compensating apparatus, the phase comparing apparatus configured to compare the phase of the reference clock signal with the phase of the feedback clock signal, thereby generating a phase comparison signal; and
a delay control apparatus coupled with the phase comparing apparatus, the delay control apparatus configured to generate the delay control signal in response to the phase comparison signal, wherein
the frequency adjusting apparatus includes:
a frequency control signal generating unit configured to divide the frequency of the reference clock signal by a plurality of division ratios to generate a multi-bit frequency control signal; and
a frequency adjusting unit configured to adjust the frequency of the reference clock signal in response to the multi-bit frequency control signal.
6. The DLL circuit of claim 5 , wherein the frequency control signal generating unit is configured to generate the multi-bit frequency control signal, which is cyclically changed in logical value bit by bit, in response to the reference clock signal.
7. The DLL circuit of claim 5 , wherein the frequency adjusting unit cyclically is configured to increase or decrease a delay time to be applied to the reference clock signal according to a cyclical change in the logical value of the frequency control signal.
8. The DLL circuit of claim 5 , further comprising a clock signal input buffer configured to buffer an external clock signal and generate the reference clock signal.