IP Library Granted Patent US 8,586,876
Granted Patent B2
US 8,586,876 · App. 13/085,804 · Granted Nov 19, 2013

Laminated circuit board and board producing method

Inventor: Hideaki Yoshimura (Kawasaki, JP)
Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,586,876
App. No.
13/085,804
Granted
Nov 19, 2013
Kind
B2
Abstract

A laminated circuit board includes a first wiring board that has a first land formed on a surface thereof; a second wiring board that has a second land formed on a surface thereof; a bonding layer that is made of a bonding resin, being laid between the first wiring board and the second wiring board, wherein the bonding layer electrically connects the first land and the second land via a conducting material; and a plate that has a through-hole into which the conducting material is supplied, wherein the plate has a resin accommodating space that accommodates therein an excess bonding resin that appears during layer stacking.

Claims (23)

1. A laminated circuit board comprising:

a first wiring board that has a first land formed on a surface thereof;

a second wiring board that has a second land formed on a surface thereof;

a bonding layer that is made of a bonding resin, being laid between the first wiring board and the second wiring board, wherein the bonding layer electrically connects the first land and the second land via a conducting material; and

a plate that has a through-hole into which the conducting material is supplied, wherein

the plate has a resin accommodating space that accommodates therein an excess bonding resin that appears during layer stacking, the resin accommodating space having a total volume equal to a volume calculated using a residual copper ratios of wiring surfaces of the first and the second wiring boards.

2. The laminated circuit board according to claim 1 , wherein the resin accommodating space is a through-hole.

3. The laminated circuit board according to claim 1 , wherein the bonding layer is formed on each of the front surface and the rear surface of the plate in advance.

4. The laminated circuit board according to claim 2 , wherein the bonding layer is formed on each of the front surface and the rear surface of the plate in advance.

5. The laminated circuit board according to claim 3 , wherein a bonding surface of the bonding layer that is formed on each of the front surface and the rear surface of the plate is covered with a protective film.

6. The laminated circuit board according to claim 3 , wherein a bonding layer that is formed on either the front surface or the rear surface of the plate has a through-hole that accommodates therein the excess bonding resin but the other bonding layer does not.

7. The laminated circuit board according to claim 4 , wherein a bonding layer that is formed on either the front surface or the rear surface of the plate has a through-hole that accommodates therein the excess bonding resin but the other bonding layer does not.

8. The laminated circuit board according to claim 1 , wherein the through-hole of the plate is filled with the conducting material in advance to connect the first land and the second land.

9. The laminated circuit board according to claim 2 , wherein the through-hole of the plate is filled with the conducting material in advance to connect the first land and the second land.

10. The laminated circuit board according to claim 3 , wherein the through-hole of the plate is filled with the conducting material in advance to connect the first land and the second land.

11. The laminated circuit board according to claim 4 , wherein the through-hole of the plate is filled with the conducting material in advance to connect the first land and the second land.

12. The laminated circuit board according to claim 5 , wherein the through-hole of the plate is filled with the conducting material in advance to connect the first land and the second land.

13. A method of producing a laminated circuit board, the method comprising:

forming bonding layers on bonding surfaces of a first wiring board and a second wiring board, wherein the first wiring board has a first land formed on the surface thereof, the second wiring board has a second land formed on the surface thereof, and the bonding layers electrically connect the first land and the second land via a conducting material;

forming a through-hole on the bonding layers to accommodate the conducting material;

filling the through-hole with the conducting material;

aligning a plate to a bonding plane where the first wiring board and the second wiring board are bonded together, wherein the plate has a resin accommodating space that accommodates therein an excess bonding resin that appears during layer stacking, the resin accommodating space having a total volume equal to a volume calculated using a residual copper ratios of wiring surfaces of the first and the second wiring boards; and

applying heat under pressure to perform the layer stacking, wherein the pressure is in a direction perpendicular to the plate position-decided at the deciding and layers of the first wiring board and the second wiring board.

Assignments (3)
CHANGE OF NAME Recorded Jun 6, 2023
From: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
To: FICT LIMITED
Reel/Frame 063881/0638 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2020
From: FUJITSU LIMITED
To: FUJITSU INTERCONNECT TECHNOLOGIES LIMITED
Reel/Frame 052345/0603 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2011
From: YOSHIMURA, HIDEAKI
To: FUJITSU LIMITED
Reel/Frame 026121/0544 →
Priority Claims (1)
JP 2010-132395 · Jun 9, 2010 · national
Continuity (1)
Related Publication 20110303454A1 · Dec 15, 2011