CMOS image sensor with built in correction for column failure
View Patent ↗A system for correcting a column line failure in an imager includes a pixel selection circuit configured to receive three adjacent pixel output signals, P(n−1), P(n) and P(n+1), respectively, from three adjacent column lines, (n−1) th column line, n th column line and (n+1) th column line. The (n−1) th column line is disposed left of an n th column line, and the (n+1) th column line is disposed right of the n th column line. A generator for generating a bit pattern is also included for indicating a column line failure in the three adjacent column lines. The pixel selection circuit is configured to provide a pixel output signal from one of the three adjacent column lines, based on the bit pattern.
1. A system for correcting a column line failure in an imager comprising:
an array of CMOS active pixels arranged in rows and columns, wherein the array of CMOS active pixels captures color images;
a pixel selection circuit that receives three adjacent pixel output signals, P(n−1), P(n) and P(n+1), respectively, from three adjacent column lines, (n−1)th column line, nth column line and (n+1)th column line,
the (n−1)th column line disposed left of an nth column line, and the (n+1)th column line disposed right of the nth column line, and
a pattern generator that generates a bit pattern denoting a column line failure in the three adjacent column lines based on whether the column line failure occurs in an even column or an odd column,
wherein the pixel selection circuit outputs a pixel output signal from one of the three adjacent column lines, based on the bit pattern and a bit value of a first column line,
wherein the pixel selection circuit shifts the pixel output signal to the left when the column line failure occurs in an even column and shifts the pixel output signal to the right when the column line failure occurs in an odd column.
2. The system of claim 1 wherein
when the pattern generator provides a bit pattern of 0 for the nth column line, then the pixel selection circuit is configured to provide a pixel output signal from the nth column line.
3. An averaging/summing system for an imager with built-in column correction comprising:
an array of CMOS active pixels arranged in rows and columns, wherein the array of CMOS active pixels captures color images;
a pixel selection circuit that receives three adjacent pixel output signals, P(n−1), P(n) and P(n+1), respectively, from three adjacent column lines, (n−1)th column line, nth column line and (n+1)th column line,
the (n−1)th column line disposed left of an nth column line, and the (n+1)th column line disposed right of the nth column line,
a pattern generator that generates a bit pattern denoting a column line failure in a column line of the imager, wherein each respective column line is assigned a bit value of 1 or 0 in the bit pattern, and
an amplifier selection circuit that receives an averaging/summing command and the bit pattern,
wherein when the averaging/summing command is asserted, the amplifier selection circuit connects an amplifier in one column line with another amplifier in an adjacent column line, based on the bit pattern, wherein when the averaging/summing command is asserted at a first value the amplifiers are connected in a first configuration to average signals on their respective column lines, and wherein when the averaging/summing command is asserted at a second value the amplifiers are connected in a second configuration to sum signals on their respective column lines; and
wherein when the bit pattern generator provides a first bit pattern, pixels from the (n−1)th column line and the nth column line are averaged/summed, and wherein when the bit pattern generator provides a second bit pattern, pixels from the nth column line and the (n+1)th column line are averaged/summed.
4. The averaging/summing system of claim 3 wherein
the amplifier selection circuit is configured to connect an amplifier in the nth column with another amplifier in the (n−1)th column line, when the bit pattern includes a value of 1 for the nth column line and a value of 1 for the (n−1)th column line.
5. The averaging/summing system of claim 4 wherein
n is an odd numbered column.
6. The averaging/summing system of claim 3 wherein
the amplifier selection circuit is configured to connect an amplifier in the nth column with another amplifier in the (n+1)th column line, when the bit pattern includes a value of 0 for the nth column line and n is an odd numbered column.
7. The averaging/summing system of claim 3 wherein
the amplifier selection circuit is configured to not connect an amplifier in the nth column with another amplifier in the (n−1)th column line or the (n+1)th column line, when the bit pattern includes a value of 1 for the nth column line and a value of 0 for the (n−1)th column line.
8. A method for correcting a column line failure in an imager having an array of CMOS active pixels arranged in rows and columns, wherein the method comprises:
with the array of CMOS active pixels, capturing a color image;
with a pixel selection circuit, receiving three adjacent pixel output signals, P(n−1), P(n) and P(n+1), respectively, from three adjacent column lines, (n−1)th column line, nth column line and (n+1)th column line, in which the (n−1)th column line is disposed left of an nth column line, and the (n+1)th column line is disposed right of the nth column line;
with a pattern generator, generating a bit pattern denoting a column line failure in the three adjacent column lines based on whether the column line failure occurs in an even column or an odd column; and
outputting a pixel output signal from one of the three adjacent column lines, based on the bit pattern and a bit value of a first column line,
wherein the pixel selection circuit shifts the pixel output signal to the left when the column line failure occurs in an even column and shifts the pixel output signal to the right when the column line failure occurs in an odd column.
9. The method of claim 8 wherein the outputting step includes:
when the pattern generator provides a bit pattern of 0 for the (n−1)th column line and 1 for the nth column line, then providing a pixel output signal from the (n+1)th column line.
10. The method of claim 9 including the step of:
connecting successive pixel output signals, disposed to the right of the nth column line, to successive column lines disposed to the right of the (n+1)th column line, respectively.
11. The method of claim 8 wherein the outputting step includes:
when the pattern generator provides a bit pattern of 1 for the (n−1)th column line and 1 for the nth column line, then providing a pixel output signal from the (n−1)th column line.
12. The method of claim 11 including the step of:
connecting successive pixel output signals, disposed to the left of the nth column line, to successive column lines disposed to the left of the (n−1)th column line, respectively.
13. The method of claim 8 wherein the outputting step includes:
when the pattern generator provides a bit pattern of 0 for the nth column line, then providing a pixel output signal from the nth column line.
14. The method of claim 8 including the steps of:
receiving an averaging/summing command, and
when the averaging/summing command is active, connecting an amplifier in one column line with another amplifier in an adjacent column line, based on the bit pattern.