Multilayer interconnect structure and method for integrated circuits

1. A method for forming an integrated circuit (IC) having a multilayer interconnect structure, comprising:

supplying a substrate having thereon an N th dielectric, in or on which it is desired to form a multi-layer interconnection having lower conductor M N , upper conductor M N+1 and interconnecting via V N+1/N ;

forming the lower conductor M N on the substrate with an upper surface of the lower conductor M N recessed below an upper surface of the N th dielectric;

providing an (N+1) th dielectric above the N th dielectric and the upper surface of the lower conductor M N ;

etching an (N+1) th cavity through the (N+1) th dielectric from a desired location of the upper conductor M N+1 and exposing the upper surface of the lower conductor M N ;

filling the (N+1) th cavity with an electrical conductor adapted to form the upper conductor M N+1 and the connecting via V N+1/N , and make electrical contact with the upper surface of the lower conductor M N ; and

determining whether or not a desired multilevel interconnection stack having N=Q total interconnection levels is complete, and if not:

optionally removing conductor material in the (N+1) th cavity to lower an upper surface of the upper conductor M N+1 below an upper surface of the (N+1) th dielectric; and then

incrementing N by one and repeating providing, etching, filling, querying, and removing for any or all desired successive interconnection level N up to N=Q−1.

2. The method of claim 1 , further comprising, after N=Q−1, incrementing N by one and repeating at least providing, etching, and filling for interconnection level N=Q.

3. The method of claim 1 , wherein removing conductor material in the (N+1) th cavity to lower an upper surface of the upper conductor M N+1 below an upper surface of the (N+1) th dielectric is accomplished by chemical-mechanical-polishing (CMP).

4. The method of claim 1 , wherein removing conductor material in the (N+1) th cavity to lower an upper surface of the upper conductor M N+1 below an upper surface of the (N+1) th dielectric is accomplished by etching an exposed surface of the upper conductor M N+1 .

5. The method of claim 1 , wherein removing conductor material in the (N+1) th cavity to lower an upper surface of the upper conductor M N+1 below an upper surface of the (N+1) th dielectric is accomplished by converting conductive material near an exposed upper surface of the upper conductor M N+1 to an oxide of the conductive material and then removing the oxide by etching.

6. The method of claim 1 , wherein forming the lower conductor M N comprises:

forming at least an N th dielectric on the substrate;

etching an N th cavity at least through the N th dielectric, corresponding to the desired location of the lower conductor M N ;

filling the N th cavity with electrically conductive material adapted to serve as the lower conductor M N ; and

removing conductive material in the N th cavity to lower an upper surface of the lower conductor M N below an upper surface of the N th dielectric within a recess portion of the N th dielectric around the N th cavity.

7. The method of claim 6 , wherein removing conductive material in the N th cavity to lower an upper surface of the lower conductor M N below an upper surface of the N th dielectric within a recess portion of the N th dielectric around the N th cavity is accomplished by chemical-mechanical-polishing (CMP).

8. The method of claim 1 , wherein removing conductive material in the N th cavity to lower an upper surface of the lower conductor M N below an upper surface of the N th dielectric within a recess portion of the N th dielectric around the N th cavity is accomplished by etching an exposed surface of the upper conductor M N+1 .

9. The method of claim 1 , wherein removing conductive material in the N th cavity to lower an upper surface of the lower conductor M N below an upper surface of the N th dielectric within a recess portion of the N th dielectric around the N th cavity is accomplished by converting conductive material near an exposed upper surface of the lower conductor M N to an oxide of the conductive material and then removing the oxide by etching.

10. A method for forming a multi-layer interconnection, comprising:

providing a substrate having thereon a first dielectric for supporting the multi-layer interconnection, wherein the multi-layer interconnection has a lower conductor M N , upper conductor M N+1 , an interlayer dielectric and interconnecting via conductor V N+1/N ;

wherein the lower conductor M N has a first upper surface located in a recess below a second upper surface of the first dielectric;

forming the interlayer dielectric above the first and second surfaces;

etching a cavity through the interlayer dielectric from a desired location of the upper conductor M N+1 and exposing the first surface in the recess; and

filling the cavity with an electrical conductor to form the upper conductor M N+1 and the connecting via conductor V N+1/N making electrical contact between a first of upper conductor M N+1 and the first upper surface in the recess; and

removing excess electrical conductor overlying the interlayer dielectric, thereby electrically separating the first and a second of upper conductor M N+1 .

11. The method of claim 10 , further comprising, recessing an upper surfaces of the first and the second of upper conductor M N+1 below an upper surface of the interlayer dielectric.

12. The method of claim 11 , wherein recessing is performed by oxidation and oxide etching of the electrical conductor.