Circuit and method for reducing the propagation of single event transient effects
View Patent ↗Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages.
1. A radiation hardened latch circuit comprising:
a first latch stage comprising a first N-channel cascode stage, a second N-channel cascode stage, and a first cross-coupled P-channel transistor pair, wherein the drain terminals of the first N-channel cascode stage are connected to the source terminals of the second N-channel cascode stage and the drain terminals of the second N-channel cascode stage are connected to the drain terminals of the first cross-coupled P-channel transistor pair; and
a second latch stage comprising a third N-channel cascode stage, a fourth N-channel cascode stage, and a second cross-coupled P-channel transistor pair, wherein the drain terminals of the third N-channel cascode stage are connected to the source terminals of the fourth N-channel cascode stage and the drain terminals of the fourth N-channel cascode stage are connected to the drain terminals of the second cross-coupled P-channel transistor pair;
wherein the first N-channel cascode stage is coupled to a first signal input and an inverted first signal input;
wherein the second N-channel cascode stage is coupled to a clock signal;
wherein the drain terminals of the first cross-coupled P-channel transistor pair are directly coupled to a first latch stage output;
wherein the first latch stage output is coupled to the third N-channel cascode stage; and
wherein the drain terminals of the second cross-coupled P-channel transistor pair are coupled to and a second latch stage differential output.
2. A radiation hardened latch circuit comprising:
a first latch stage comprising a first latch stage data input, a first clock signal input, a first cross-coupled P-channel transistor pair, and a first latch stage output;
a second latch stage comprising a second latch stage input and a second latch stage output;
a third latch stage comprising a third latch stage data input, an inverted clock signal input, and a third latch stage output; and
a fourth latch stage;
wherein the first cross-coupled P-channel transistor pair is directly coupled to the second latch stage input;
wherein the second latch stage comprises a P-channel transistor pair, but not an N-channel cascode stage and the second latch stage output is directly coupled to the third latch stage data input;
wherein the third latch stage comprises a P-channel transistor pair and at least one N-channel cascode stage and the third latch stage output is directly coupled to the fourth latch stage; and
the fourth latch stage comprises a P-channel transistor pair, but not an N-channel cascode stage.
3. The radiation hardened latch circuit of claim 2 , wherein the first latch stage receives the first data signal input directly through an inverter.
4. The radiation hardened latch circuit of claim 2 , wherein the first latch stage data input and the third latch stage data input comprise differential inputs.
5. The radiation hardened latch circuit of claim 2 , wherein the first latch stage output and the third latch stage output comprise differential outputs.
6. The radiation hardened latch circuit of claim 2 , wherein the second latch stage input is a differential input and the second latch stage output is a differential output.