Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making
A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.
1. A semiconductor device comprising:
a substrate layer of a semiconductor material of a first conductivity type;
a channel layer of a semiconductor material of the first conductivity type above an upper surface of the substrate layer, the channel layer comprising one or more raised regions extending upward from adjacent surfaces of the channel layer, the one or more raised regions each comprising an upper surface and first and second sidewalls, wherein the first and second sidewalls of the one or more raised regions taper inward to form an angle of at least 5° from vertical to the upper surface of the substrate layer, wherein the one or more raised regions each comprises implanted regions of a semiconductor material doped with dopants that impart, to the semiconductor material of the raised regions, conductivity of a second conductivity type different than the first conductivity type, wherein each of the implanted regions is adjacent to respective of the first and second sidewalls and extends beneath a respective of the adjacent surfaces of the channel layer to form a gate region; and
a source layer of a semiconductor material of the first conductivity type on the upper surface of each of the one or more raised regions;
wherein the implanted regions of the one or more raised regions are downwardly offset from respective of the source layers such that the dopants that impart conductivity of a second conductivity type are not implanted within the respective of the source layers.
2. The semiconductor device of claim 1 , wherein each of the implanted regions of the one or more raised regions are offset from respective of the source layers by a region of semiconductor material of the first conductivity type having a doping concentration which is substantially the same as a doping concentration of an inner region of the one or more raised regions.
3. The semiconductor device of claim 1 , wherein the source layer and the implanted regions of the one or more raised regions each have a doping concentration of at least 1×10 19 cm −3 .
4. The semiconductor device of claim 1 , wherein the implanted regions of the one or more raised regions are offset from respective of the source layers by 0.5 μm or less.
5. The semiconductor device of claim 1 , wherein:
each of the implanted regions of contacts the upper surface of the one or more raised regions;
the source layer is on an inner portion of the raised region; and
the device further comprises an oxide on the upper surface of the raised region adjacent the implanted regions of the one or more raised regions.
6. The semiconductor device of claim 1 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <5° from vertical to the upper surface of the substrate layer.
7. The semiconductor device of claim 1 , wherein each of the first and second sidewalls taper inward and form an angle of at least 5° from vertical to the upper surface of the substrate layer for at least half of the distance between a lower surface of at least one of respective of the gate regions and the upper surface of respective of the one or more raised regions.
8. The semiconductor device of claim 1 , wherein the vertical distance between a lower surface of the channel layer and each of the upper surfaces of the one or more raised regions is 0.5 to 5 μm and wherein the channel layer has a doping concentration of 1×10 16 to 1×10 18 cm −3 outside the implanted regions.
9. The semiconductor device of claim 1 , wherein the substrate has a thickness of 100 to 500 μm and a doping concentration of 1×10 19 to 5×10 19 cm −3 .
10. The semiconductor device of claim 1 , wherein the source layer has a thickness of 0.1 to 1.0 μm and a doping concentration of 1×10 18 to 1×10 20 cm −3 .
11. The semiconductor device of claim 1 , wherein the implanted regions of the one or more raised regions and the gate regions each have a doping concentration of 5×10 18 to 1×10 20 cm −3 .
12. The semiconductor device of claim 1 , further comprising a drift layer of a semiconductor material of the first conductivity type between the substrate and the channel layer.
13. The semiconductor device of claim 12 , wherein the drift layer has a thickness of 5 to 100 μm and a doping concentration of 1×10 14 to 2×10 16 cm −3 .
14. The semiconductor device of claim 1 , further comprising a buffer layer between the substrate and the channel layer.
15. The semiconductor device of claim 14 , wherein the buffer layer has a thickness of 0.1 to 1 μm and a doping concentration of 5×10 17 to 5×10 18 cm −3 .
16. The semiconductor device of claim 1 , wherein the device comprises a plurality of raised regions, wherein the plurality of raised regions are elongate and are arranged in spaced relationship as fingers.
17. The semiconductor device of claim 1 , wherein:
the semiconductor material of the first conductivity type is an n-type semiconductor material;
the semiconductor material of the second conductivity type is a p-type semiconductor material; and
the dopants that impart conductivity of the second conductivity type comprise aluminum ions.
18. The semiconductor device of claim 1 , wherein the semiconductor material is a wide band-gap semiconductor material.
19. The semiconductor device of claim 1 , further comprising:
a first gate contact on a first of the adjacent surfaces of the channel layer;
a source contact on the source layer; and
a drain contact on a surface of the substrate layer opposite the channel layer.
20. A method comprising:
selectively implanting ions into a channel layer of a semiconductor material of a first conductivity type to form implanted gate regions doped with dopants that impart, to the semiconductor material semiconductor material, of a second conductivity type different than the first conductivity type, wherein the channel layer is above an upper surface of a substrate layer and wherein the channel layer comprises one or more raised regions extending upward from adjacent surfaces of the channel layer, the one or more raised regions each comprising an upper surface and first and second sidewalls, wherein the first and second sidewalls of the one or more raised regions taper inward to form an angle of at least 5° from vertical to the upper surface of the substrate layer, wherein a source region of a semiconductor material of the first conductivity type is on the upper surface of each of the one or more raised regions, each of the source regions comprising side surfaces adjacent the first and second sidewalls and an upper surface, wherein an implant mask is on the upper surface of the source regions during the implanting of the ions and the implanted gate regions are formed in the sidewalls and in the adjacent surfaces of the channel layer, wherein the implanted gate regions are downwardly offset from respective of the upper surfaces of the one or more raised regions so that the dopants that impart conductivity of a second conductivity type are not implanted within a respective source region; and
removing the implant mask.