Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
1. A device comprising:
a first conductive line and a second conductive line;
a first memory cell string coupled between the first conductive line and the second conductive line;
a first select transistor coupled between the first conductive line and the first memory cell string;
a second memory cell string coupled between the first conductive line and the second conductive line;
a first bipolar junction transistor coupled between the first memory cell string and the second conductive line;
a second bipolar junction transistor coupled between the second memory cell string and the second conductive line;
a second select transistor coupled between the first conductive line and the second memory cell string; and
wherein the first conductive line comprises a data line of the device, and the second conductive line comprises a source line of the device.
2. The device of claim 1 , wherein the first bipolar junction transistor includes a first base, and the second bipolar junction transistor includes a second base coupled to the first base.
3. The device of claim 2 , further comprising:
a third memory cell string coupled between the first conductive line and the second conductive line; and
a third bipolar junction transistor coupled between the third memory cell string and the second conductive line, wherein the third bipolar junction transistor includes a third base uncoupled to the first base and the second base.
4. A device comprising:
a first conductive line and a second conductive line, wherein the first conductive line comprises a data line of the device, and the second conductive line comprises a source line of the device;
a first memory cell string coupled between the first conductive line and the second conductive line;
a second memory cell string coupled between the first conductive line and the second conductive line;
a first bipolar junction transistor coupled between the first memory cell string and the second conductive line;
a second bipolar junction transistor coupled between the second memory cell string and the second conductive line;
a third memory cell string coupled between the first conductive line and the second conductive line; and
a third bipolar junction transistor coupled between the third memory cell string and the second conductive line, wherein the third bipolar junction transistor includes a third base uncoupled to the first base and the second base.
5. A device comprising:
a first conductive line and a second conductive line;
a first memory cell string coupled between the first conductive line and the second conductive line;
a second memory cell string coupled between the first conductive line and the second conductive line;
a first bipolar junction transistor coupled between the first memory cell string and the second conductive line;
a second bipolar junction transistor coupled between the second memory cell string and the second conductive line;
a first select transistor coupled between the first conductive line and the first memory cell string; and
a second select transistor coupled between the first conductive line and the second memory cell string, wherein the first select transistor includes a gate uncoupled to a gate of the second select transistor.
6. A device comprising:
a first region having a semiconductor material of a first type;
gates located along a length of the first region, each of the gates being separated from the first region by a respective charge storage structure;
a second region having a semiconductor material of the first type;
a third region coupling the first region to the second region, the third region having a semiconductor material of a second type; and
a conductive line directly coupled to the third region, wherein the first region forms an emitter of a bipolar junction transistor, the second region forms a collector of the bipolar junction transistor, and the third region forms a base of the bipolar junction transistor.
7. The device of claim 6 , wherein the first type includes p-type silicon.
8. The device of claim 7 , wherein the second type includes n-type silicon.
9. A device comprising:
a first region having a semiconductor material of a first type;
gates located along a length of the first region, each of the gates separated from the first region by a respective charge storage structure;
a second region having a semiconductor material of the first type;
a third region coupling the first region to the second region, the third region having a semiconductor material of a second type;
a conductive line directly coupled to the third region; and
a source line directly coupled to the second region.
10. The device of claim 9 , wherein the first region, the second region, and the third region are configured to form at least a part of a bipolar junction transistor.
11. The device of claim 9 , further comprising a substrate, wherein the second region line overlies the substrate, the third region overlies the second region, and the first region overlies the third region.
12. The device of claim 11 , further comprising a select transistor coupled to and overlying the first region, wherein the select transistor comprises a field effect transistor.
13. A device comprising:
a first region having a semiconductor material of a first type;
gates located along a length of the first region, each of the gates being separated from the first region by a respective charge storage structure;
a second region having a semiconductor material of the first type;
a third region coupling the first region to the second region, the third region having a semiconductor material of a second type; and
a conductive line directly coupled to the third region, wherein the first region forms a collector of a bipolar junction transistor, the second region forms an emitter of the bipolar junction transistor, and the third region forms a base of the bipolar junction transistor.
14. The device of claim 13 , wherein the first type includes n-type silicon.
15. The device of claim 14 , wherein the second type includes p-type silicon.