Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof
A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The memory elements of the multiple layers are formed simultaneously in an orientation parallel to the substrate thereby reducing processing cost. In another aspect, a diode is formed in series with each memory element to reduce current leakage. The diode is incorporated within a pillar line acting as a bit line without taking up additional space.
1 . A memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate, the memory further comprising:
a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;
a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes;
a plurality of non-volatile re-programmable memory elements individually connected between the bit line pillars and the word lines adjacent the crossings thereof; and wherein
at each crossing between a bit line pillar and a word line, each non-volatile reprogrammable memory elements further comprises a first layer and a second layer stacked along the y-direction at the crossing with the first layer making electrical contact with a surface of a bit line pillar and the second layer making electrical contact with a surface of a word line.
2 . The memory as in claim 1 , wherein:
said first layer is a metal oxide layer with oxygen vacancies; and
said second layer is a metal layer acting as an electrode with a high work function.
3 . The memory of claim 1 , wherein the individual memory elements include at least one of a carbon material or a phase change material.
4 . The memory of claim 1 , wherein the individual memory elements are characterized by a level of electrical conductance that changes in response to an electrical stimulus applied thereto.
5 . The memory as in claim 1 , wherein:
the word lines are low melting-point metal including aluminum or copper.
6 . The memory as in claim 1 , wherein:
the word lines are high melting-point metal including titanium.
7 . The memory as in claim 1 , wherein:
said plurality of parallel planes stacked in the z-direction has a top surface and a bottom surface; and
a word line in a plane is accessed from the top surface via a conductive riser column connected to the word line.
8 . The memory as in claim 1 , wherein:
said plurality of parallel planes stacked in the z-direction has a top surface and a bottom surface; and
a word line in a plane is accessed from the bottom surface via a first conductive riser column to the top surface, followed by a metal bridge on the top surface, followed by a second conductive riser column connected to the word line.
9 . The memory as in claim 1 , further comprising:
a plurality of metal lines; and
select devices arranged to switch a selected row of local bit line pillars in the x-direction to individual ones of the metal lines.
10 . The memory as in claim 1 , wherein the plurality of select devices and the plurality of third conductive lines are formed the a semiconductor substrate.
11 . The memory as in claim 1 , wherein the first and second layers have dimensions in the x-z plane commensurate with a y-direction projection of the bit line pillar on the word line at the crossing.
12 . The memory as in claim 1 , further comprising:
a diode in series between each non-volatile reprogrammable memory element and a respective bit line pillar.
13 . The memory as in claim 12 , wherein said diode is physically fully integrated into the bit line pillar at the crossing.
14 . The memory as in claim 12 , wherein said diode has a PN junction constituted from the bit line pillar having P+ doping throughout except for a localized region of N+ doping at the crossing.
15 . The memory as in claim 12 , wherein said diode has a PN junction constituted from the bit line pillar having N+ doping throughout except for a localized region of P+ doping at the crossing.
16 . The memory as in claim 1 , wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.
17 . A method of forming a memory having memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, comprising:
providing a semi-conductor substrate;
forming predetermined active elements and metal lines on the semi-conductor substrate;
forming a multi-layer structure on top of the substrate, the multi-layer structure being alternate layers of a dielectric and a sacrificial material to form gross stratified layers corresponding to the multiple layers;
forming a 2-D array in the x-y plane of conductive pillars elongated in the z-direction through the plurality of planes;
exposing a cross section of the gross stratified layers by opening a plurality of trenches in the multi-layer structure;
etching recesses in the sacrificial layer of the multi-layers to access the conductive pillars from each of the trenches; and
forming layers of the memory elements on the multiple planes in a lateral direction in the recesses of the designated mutely-layers simultaneously.
18 . The method as in claim 17 , further comprising:
forming metal lines over the layers of the memory elements.
19 . The method as in claim 17 , wherein:
the conductive pillars are formed from polysilicon; and the method further comprises:
doping the polysilicon with P+ dopant; and
before said forming the layers of the memory elements, doping each region of the conductive pillar exposed by the recesses with N+ dopant to form a diode.
20 . The method as in claim 17 , wherein:
the conductive pillars are formed from polysilicon; and the method further comprises:
doping the polysilicon with N+ dopant; and
before said forming the memory elements, doping each region of the conductive pillar exposed by the recesses with P+ dopant to form a diode.