IP Library Granted Patent US 8,928,792
Granted Patent B1
US 8,928,792 · App. 13/153,369 · Granted Jan 6, 2015

CMOS image sensor with global shutter, rolling shutter, and a variable conversion gain, having pixels employing several BCMD transistors coupled to a single photodiode and dual gate BCMD transistors for charge storage and sensing

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Quick Facts
Patent No.
US 8,928,792
App. No.
13/153,369
Granted
Jan 6, 2015
Kind
B1
Abstract

The invention describes a solid-state CMOS image sensor array and discloses image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for a single photodiode, for charge storage and sensing. Thus, the valuable pixel area saved by employing the BCMD transistor for charge storage and sensing is used by placing several BCMD transistors coupled to one photodiode. This increases the Dynamic Range (DR) of the sensor, since the same photodiode can integrate charge for different integration times, both long and short. This allows sensing of two different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. The signal processing circuits located at the periphery of the array can then process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed is an image sensor array with pixels that use BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors by applying various biases to the gates. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and the same structure can be used to detect, at the same time, low level signals with high conversion gain and thus low noise.

Claims (13)

1. A CMOS image sensor pixel array, wherein each pixel of the array includes at least one pixel circuit, comprising:

at least two Bulk Charge Modulated Device (BCMD) transistors coupled to a single photodiode, wherein said BCMD transistors have the capability of storing charge transferred from the photodiode for all the pixels of the array simultaneously, thereby performing the global shuttering function;

said stored charge being accumulated in said photodiodes during at least two different integration times;

peripheral circuitry; and

first and second transfer gates, wherein the first transfer gate is electrically connected between the photodiode and a first one of the BCMD transistors, wherein the second transfer gate is electrically connected between the photodiode and a second one of the BCMD transistors, and wherein each of the BCMD transistors has a gate electrically connected to a row address line.

2. The CMOS image sensor array of claim 1 wherein said BCMD transistors include independently addressed input and reset gates.

3. The CMOS image sensor array of claim 1 wherein said at least two BCMD transistors further include concentric dual-gate BCMD transistors, wherein said gates are biased at suitable levels to change the BCMD transistor conversion gain, thereby providing sensors having an improved dynamic range.

4. The CMOS image sensor array of claim 1 wherein said BCMD transistors have the capability of storing charge transferred from said photodiode for all the pixels of the array in a row by row manner, thereby performing the rolling shuttering function.

5. The CMOS image sensor of claim 4 wherein said BCMD transistors include independently addressed input and reset gates.

6. The CMOS image sensor array of claim 4 wherein said at least two BCMD transistors further include concentric dual-gate BCMD transistors, wherein said gates are biased at suitable levels to change the BCMD transistor conversion gain, thereby providing sensors having an improved dynamic range.

7. The CMOS image sensor pixel array of claim 1 wherein said photodiode has incorporated therein a JFET anti-blooming structure to drain away any overflow charge.

8. The CMOS image sensor array of claim 1 wherein said photodiode has incorporated therein a MOSFET anti-blooming structure to drain away any overflow charge.

9. The CMOS image sensor array of claim 1 wherein said peripheral circuitry performs a signal differencing function on said charge accumulated in said photodiode during at least two different integration times, thus providing for detection of intra-scene motion.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034673/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2012
From: HYNECEK, JAROSLAV; AGRANOV, GENNADIY; LI, XIANGLI; KOMORI, HIROFUMI; ZHAO, XIA; WAN, CHUNG CHUN
To: APTINA IMAGING CORPORATION
Reel/Frame 027637/0936 →