Semiconductor integrated circuit
View Patent ↗Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P 1 -P 8 . The peripheral wiring is formed on the semiconductor substrate and is made of a metal layer that is the same layer as or an upper layer of a metal layer forming the pad electrodes P 1 -P 8 , or a polysilicon layer. A power supply electric potential Vcc is applied to a first end of the peripheral wiring, while a ground electric potential Vss is applied to a second end of the peripheral wiring through a resistor R 2 . A detection circuit is connected to a connecting node N 1 between the peripheral wiring and the resistor R 2 , and is structured to generate an anomaly detection signal ERRFLG based on an electric potential at the connecting node N 1.
1. A semiconductor integrated circuit comprising:
a semiconductor substrate;
a circuit region formed in a surface of the semiconductor substrate;
a pad electrode formed on the surface of the semiconductor substrate and connected with a circuit in the circuit region;
a re-distribution wiring formed on the surface of the semiconductor substrate and connected to the pad electrode;
a resin layer formed on the surface of the semiconductor substrate so as to cover the re-distribution wiring;
a protruded electrode connected to the re-distribution wiring through an opening in the resin layer;
a peripheral wiring having a first end and a second end and disposed along a periphery of the semiconductor substrate outside the circuit region, a first electric potential being applied to the first end;
a resistor connected between the second end of the peripheral wiring and a second electric potential; and
a detection circuit generating an anomaly detection signal based on an electric potential at a connecting node between the peripheral wiring and the resistor.
2. The semiconductor integrated circuit of claim 1 , further comprising an output transistor outputting a data signal from a circuit in the circuit region, and an output control circuit disabling outputting of the data signal from the output transistor in accordance with the anomaly detection signal generated by the detection circuit.
3. The semiconductor integrated circuit of claim 1 , further comprising an operation halt signal generation circuit generating an operation halt signal to halt an operation of the circuit in the circuit region in accordance with the anomaly detection signal generated by the detection circuit.
4. The semiconductor integrated circuit of claim 3 , further comprising a control circuit controlling the operation halt signal generation circuit so that the operation halt signal is not generated.
5. The semiconductor integrated circuit of claim 1 , wherein the detection circuit comprises an inverter, an input terminal of the inverter being connected to the connecting node.
6. The semiconductor integrated circuit of claim 1 , wherein the detection circuit comprises a comparator having a first input terminal and a second input terminal, the connecting node being connected to the first input terminal and a reference electric potential being applied to the second input terminal.
7. The semiconductor integrated circuit of claim 1 , wherein the peripheral wiring is made of a metal wiring or a polysilicon wiring disposed on the surface of the semiconductor substrate.
8. The semiconductor integrated circuit of claim 1 , wherein the peripheral wiring is made of a diffusion layer formed in the surface of the semiconductor substrate.