IP Library Granted Patent US 8,669,606
Granted Patent B2
US 8,669,606 · App. 13/156,766 · Granted Mar 11, 2014

Semiconductor device and method for manufacturing thereof

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Quick Facts
Patent No.
US 8,669,606
App. No.
13/156,766
Granted
Mar 11, 2014
Kind
B2
Abstract

An embodiment of the invention includes a semiconductor device including a semiconductor substrate with a trench; a tunnel insulating film covering an inner surface of the trench; a trap layer in contact with the tunnel insulating film on an inner surface of an upper portion of the trench; a top insulating film in contact with the trap layer; a gate electrode embedded in the trench, and in contact with the tunnel insulating film at a lower portion of the trench and in contact with the top insulating film at the upper portion of the trench, in which the trap layer and the top insulating film, in between the lower portion of the trench and the upper portion of the trench, extend and protrude from both sides of the trench so as to be embedded in the gate electrode, and a method for manufacturing thereof.

Claims (48)

1. A semiconductor device comprising:

a semiconductor substrate comprising a trench;

a tunnel insulating film in contact with a surface of the trench;

a first trap layer comprising a first portion in contact with the tunnel insulating film within the trench, the first trap layer further comprising a second portion free of contacting the tunnel insulating film within the trench;

a first top insulating film in contact with the first trap layer; and

a gate electrode in contact with the tunnel insulating film and the first trap layer within the trench.

2. The semiconductor device of claim 1 , further comprising:

a diffusion region in the semiconductor substrate on a side of the trench.

3. The semiconductor device of claim 1 , wherein the second portion of the first trap layer and a portion of the first top insulating film protrude from a side of the trench.

4. The semiconductor device of claim 1 , wherein the gate electrode separates the first top insulating film into two sections.

5. The semiconductor device of claim 1 , wherein the first trap layer extends above the semiconductor substrate.

6. The semiconductor device of claim 1 , further comprising:

an isolation trench formed along with the trench.

7. A semiconductor device comprising:

a semiconductor substrate comprising a trench;

a tunnel insulating film in contact with a surface of the trench;

a first trap layer comprising a first portion in contact with the tunnel insulating film within the trench, the first trap layer further comprising a second portion free of contacting the tunnel insulating film within the trench;

a first top insulating film provided in contact with the first trap layer;

diffusion regions in the semiconductor substrate on both sides of the trench; and

a gate electrode in contact with the tunnel insulating film and the first trap layer within the trench,

the gate electrode is located between the tunnel insulating film and the second portion of the first trap layer.

8. The semiconductor device of claim 7 , wherein the second portion of the first trap layer and a portion of the first top insulating film protrude from a side of the trench.

9. The semiconductor device of claim 7 , wherein the gate electrode divides the first top insulating film into two segments.

10. The semiconductor device of claim 7 , further comprising:

an isolation trench formed along with the trench.

11. The semiconductor device of claim 7 , wherein each of the diffusion regions is in contact with a side of the trench.

12. The semiconductor device of claim 7 , further comprising:

a second trap layer comprising a first portion in contact with the tunnel insulating film within the trench, the second trap layer further comprising a second portion free of contacting the tunnel insulating film within the trench.

13. The semiconductor device of claim 12 , further comprising:

a second top insulating film in contact with the second trap layer.

14. A semiconductor device comprising:

a semiconductor substrate comprising a trench;

a tunnel insulating film contacting a surface of the trench;

a first trap layer comprising a first portion in contact with the tunnel insulating film in the trench, the first trap layer further comprising a second portion free of contacting the tunnel insulating film in the trench;

a first top insulating film contacting the first trap layer;

a second trap layer comprising a first portion in contact with the tunnel insulating film in the trench, the second trap layer further comprising a second portion free of contacting the tunnel insulating film in the trench;

a second top insulating film contacting the second trap layer; and

a gate electrode contacting the tunnel insulating film, the first trap layer, and the second trap layer in the trench.

15. The semiconductor device of claim 14 , further comprising:

a diffusion region in the semiconductor substrate on a side of the trench.

16. The semiconductor device of claim 14 , wherein the second portion of the first trap layer and the portion of the top insulating film protrude upwardly from a side of the trench.

17. The semiconductor device of claim 14 , wherein the gate electrode splits the first top insulating film into two parts.

18. The semiconductor device of claim 14 , further comprising:

an isolation trench formed along with the trench.

19. The semiconductor device of claim 1 , further comprising:

a second trap layer comprising a first portion in contact with the tunnel insulating film within the trench, the second trap layer further comprising a second portion free of contacting the tunnel insulating film within the trench.

20. The semiconductor device of claim 19 , further comprising:

a second top insulating film in contact with the second trap layer.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 055187/0164 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
SECURITY AGREEMENT Recorded Aug 23, 2012
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 028837/0076 →