Method for fabrication of interconnect structure with improved alignment for semiconductor devices
View Patent ↗Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned.
1. A method for forming an opening in a semiconductor device, comprising:
patterning a first hard mask layer with respect to a surface of a conductor;
patterning a second hard mask layer with respect to the surface of the conductor, wherein the second hard mask layer pattern is aligned orthogonally opposed to the first hard mask layer patterning to form a grating in a etching direction, wherein the second hard mask layer is provided in a higher layer than the first hard mask layer with respect to the surface of the conductor; and
controlling, with the grating, an etching process for exposing the surface of the conductor,
wherein the patterning of the second hard mask layer is an inversion of the patterning utilized in forming of the conductor.
2. The method of claim 1 , wherein the grating has a dimension corresponding to a critical dimension.
3. The method of claim 1 , wherein the grating is of a dimension unachievable by a conventional photolithographic process.
4. The method of claim 1 , wherein at least one of the first hard mask layer or the second hard mask layer comprising titanium nitride.
5. The method of claim 1 , wherein both the first hard mask layer or the second hard mask layer comprise titanium nitride.
6. The method of claim 1 , the etching operation further comprising selective etching.
7. A method for forming an opening in a semiconductor device, comprising:
patterning a first hard mask layer with respect to a surface of a conductor;
patterning a second hard mask layer with respect to the surface of the conductor, wherein the second hard mask layer pattern is aligned orthogonally opposed to the first hard mask layer patterning to form a grating in a etching direction; and
controlling, with the grating, an etching process for exposing the surface of the conductor,
removing, by selective anisotropic etching, a first underlying layer formed on the patterned second hard mask layer and exposing a portion of the second hard mask layer patterning.
8. The method of claim 7 , further comprising removing, by selective anisotropic etching, a second underlying layer formed between the patterned second hard mask layer and the pattern first hard mask layer and exposing a portion of the first hard mask layer patterning.
9. The method of claim 8 , further comprising removing, by selective anisotropic etching, a third underlying layer formed between the patterned first hard mask layer and the conductor exposing a portion of the surface of the conductor.
10. The method of claim 9 , wherein the controlling of the etching process with the grating further involving constraining removal of at least one of the first underlying layer, the second underlying layer, or the third underlying layer, with at least one of the exposed portion of the patterned second hard mask layer or the exposed portion of the patterned first hard mask layer.