Semiconductor device including inner interconnection structure able to conduct signals or voltages in the semiconductor chip with vertical connection vias and horizontal buried conductive lines

1. A semiconductor device comprising:

a semiconductor chip comprising a front surface with circuit elements and interconnections integrated thereon and a rear surface opposite to the front surface;

first buried conductive lines vertically separated from the front surface of the semiconductor chip;

a first conductive via connected to the first buried conductive line by piercing from the front surface of the semiconductor chip;

a second conductive via connected to the first buried conductive line through the semiconductor chip from the rear surface; and

a dielectric via disposed to electrically separate one of the buried conductive lines to a plurality of conductive line portions.

2. The semiconductor device of claim 1 , wherein the dielectric via is disposed to electrically separate one of the buried conductive lines by piercing from one of the front surface and the rear surface of the semiconductor chip.

3. The semiconductor device of claim 1 , wherein the buried conductive lines are parallel to the front surface of the semiconductor chip.

4. The semiconductor device of claim 1 , the buried conductive lines further comprising a second buried conductive line, wherein the first buried conductive line is perpendicular to the second buried conductive line.

5. The semiconductor device of claim 1 , wherein the buried conductive line comprises a conductive core part covered by an insulating layer.

6. The semiconductor device of claim 1 , wherein the buried conductive line pierces the semiconductor chip laterally.

7. The semiconductor device of claim 1 , wherein the first conductive via and the second conductive via are connected to the first buried conductive line at locations offset from each other.

8. The semiconductor device of claim 1 , further comprising:

a first connection terminal connected to a part of the first conductive via exposed at the front surface of the semiconductor chip; and

a second connection terminal connected to a part of the second conductive via exposed at the rear surface of the semiconductor chip.

9. The semiconductor device of claim 8 , wherein the first connection terminal comprises a pad connected to a through via of a second semiconductor chip stacked on the semiconductor chip.

10. The semiconductor device of claim 8 , further comprising a dielectric layer disposed to cover the rear surface of the semiconductor chip wherein the second connection terminal is exposed.

11. The semiconductor device of claim 10 , wherein the second connection terminal comprises a ball land.

12. A semiconductor device comprising:

a semiconductor chip comprising a front surface and a rear surface opposite to the front surface;

buried conductive lines comprising a first buried conductive line and a second buried conductive line, wherein the first buried conductive line is vertically separated from a second buried conductive line with respect to the front surface of the semiconductor chip;

a first conductive via connected to the first buried conductive line by piercing from the front surface of the semiconductor chip;

a second conductive via connected to the second buried conductive line through the semiconductor chip from the rear surface;

a third conductive via disposed to connect the first buried conductive line and the second buried conductive line; and

a dielectric via disposed to separate one of the buried conductive lines to a plurality of conductive line portions.

13. The semiconductor device of claim 12 , wherein the first conductive via, the second conductive via, and the third conductive via are separated from each other.

14. The semiconductor device of claim 12 , further comprising:

a first connection terminal connected to a part of the first conductive via exposed at the front surface of the semiconductor chip; and

a second connection terminal connected to a part of the second conductive via exposed at the rear surface of the semiconductor chip.

15. A semiconductor device comprising:

a semiconductor chip comprising a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals; an inner interconnection structure comprising horizontal buried conductive lines and connection vias disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals; and

a dielectric via disposed to electrically separate one of the buried conductive lines to a plurality of conductive line portions.

16. The semiconductor device of claim 15 , wherein the connection vias comprise:

a first conductive via connected to one of the buried conductive lines by piercing from the front surface of the semiconductor chip; and

a second conductive via connected to one of the buried conductive lines by piercing from the rear surface of the semiconductor chip.

17. The semiconductor device of claim 16 , wherein

the buried conductive lines comprise first buried conductive lines parallel to the front surface of the semiconductor chip and separated from each other to constitute a first array; and second buried conductive lines separated from the first array vertically and arranged across the first array to constitute a second array,

the connection vias further comprise a third conductive via disposed to interconnect the first buried conductive line and the second buried conductive line, and the semiconductor device further comprises a dielectric via disposed to selectively electrically separate one of the first buried conductive lines and the second buried conductive lines to a plurality of conductive line portions by piercing from one of the front surface and the rear surface of the semiconductor chip.