Apparatus, system, and method for using multi-level cell storage in a single-level cell mode
View Patent ↗A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.
1. A method for storing data in an electronic memory device, the method comprising:
receiving a write command to write data to an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is programmable to designated programming states, wherein each designated programming state is representative of at least two bits of data; and
programming at least one of the MLC memory elements to one of a plurality of restricted programming states in a single-level cell (SLC) mode, wherein the restricted programming states exclude at least one of the designated programming states, and the restricted programming states comprise:
a first state which is an erase state; and
a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.
2. The method of claim 1 , wherein programming the MLC memory element to one of the restricted programming states in the SLC mode further comprises programming the MLC memory element to represent a page bit within a page tuple.
3. The method of claim 2 , wherein the page bit corresponds to a most significant bit (MSB) of a bit pair corresponding to one of the designated programming states.
4. The method of claim 3 , wherein the first state represents a first binary value of the MSB, and the second state represents a second binary value of the MSB.
5. The method of claim 2 , further comprising reading the MLC memory element by determining the restricted programming state to which the MLC memory element is programmed.
6. The method of claim 5 , wherein determining the restricted programming state to which the MLC memory element is programmed further comprises performing a single read operation to determine whether the MLC memory element is programmed to the first state or the second state of the restricted programming states.
7. The method of claim 6 , wherein the MLC memory element comprises a flash memory element.
8. The method of claim 1 , wherein the restricted programming states comprise only a subset of the designated programming states to which the MLC memory element is programmable in a MLC mode.
9. The method of claim 1 , further comprising dynamically switching between a MLC mode and the SLC mode in response to a trigger event by way of not addressing one or more pages comprising certain bits of the MLC memory elements.
10. The method of claim 1 , further comprising dynamically switching between two SLC modes, wherein a first SLC mode uses a most significant bit (MSB) state to store the data, and a second SLC mode uses a least significant bit (LSB) state to store the data.
11. The method of claim 10 , further comprising dynamically switching between two SLC modes in response to a trigger event.
12. A computer program product, comprising:
a computer readable storage device to store a computer readable program, wherein the computer readable program, when executed by a processor within a computer, causes the computer to perform operations for storing data in an electronic memory device, the operations comprising:
receiving a write command to write the data to an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is programmable to 2^X designated programming states, wherein each designated programming state is representative of X bits of data, where X>1; and
programming at least one of the MLC memory elements to one of a plurality of restricted programming states in a reduced-level cell (RLC) mode to represent Y bits of the data, where Y<X, wherein the restricted programming states exclude at least one of the designated programming states, and the restricted programming states comprise:
a first state which is an erase state; and
a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.
13. The computer program product of claim 12 , wherein the computer program product, when executed by the processor within the computer, causes the computer to perform additional operations, comprising programming the MLC memory element to represent a page bit within a page tuple, wherein the page bit corresponds to a most significant bit (MSB) of a bit pair corresponding to one of the designated programming states.
14. The computer program product of claim 13 , wherein the computer program product, when executed by the processor within the computer, causes the computer to perform additional operations, comprising reading the MLC memory element by determining the restricted programming state to which the MLC memory element is programmed.
15. The computer program product of claim 14 , wherein the computer program product, when executed by the processor within the computer, causes the computer to perform additional operations, comprising performing a single read operation to determine whether the MLC memory element is programmed to the first state or the second state of the restricted programming states.
16. The computer program product of claim 12 , wherein the restricted programming states comprise only a subset of the designated programming states to which the MLC memory element is programmable in a MLC mode.
17. The computer program product of claim 12 , wherein the computer program product, when executed by the processor within the computer, causes the computer to perform additional operations, comprising dynamically switching between the SLC mode and a MLC mode in response to a trigger event by way of not addressing one or more pages comprising certain bits of the MLC memory elements.
18. The computer program product of claim 12 , wherein the computer program product, when executed by the processor within the computer, causes the computer to perform additional operations, comprising dynamically switching between two SLC modes, wherein a first SLC mode uses most significant bit (MSB) states to store the data, and a second SLC mode uses least significant bit (LSB) states to store the data.
19. A controller for an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is capable of storing at least two data bits, the controller comprising:
a physical interface to couple the controller to the electronic memory device; and
a processing unit coupled to the physical interface, the processing unit to operate the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit, wherein the restricted number of programming states comprise:
a first state which is an erase state; and
a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.
20. The controller of claim 19 , wherein the restricted programming states comprise only a subset of the designated programming states to which the MLC memory element is programmable in a MLC mode.