Nonvolatile memory device and method of operating the same

1. A nonvolatile memory device, comprising:

a plurality of latches for storing data;

a set/reset circuit for transferring data, stored in a selected latch of the latches, to a common node;

a transmission circuit for transferring the data of the common node to a first sense node;

a bit line transmission circuit for transferring the data of the first sense node to a bit line;

a sense circuit for transferring the data of the first sense node to a second sense node; and

a discharge circuit for changing a voltage level of the common node based on the data of the second sense node.

2. The nonvolatile memory device of claim 1 , wherein the sense circuit comprises an NMOS transistor for coupling the first sense node and the second sense node in response to a sense signal.

3. The nonvolatile memory device of claim 1 , wherein the precharge circuit comprises an NMOS transistor for discharging the second sense node by coupling the second sense node and a terminal of a variable voltage node, in response to a precharge signal.

4. The nonvolatile memory device of claim 3 , wherein the variable voltage of the variable voltage node is a power supply voltage or a ground voltage.

5. The nonvolatile memory device of claim 1 , wherein the discharge circuit comprises an NMOS transistor for discharging the common node based on a voltage level of the second sense node.

6. The nonvolatile memory device of claim 1 , wherein the transmission circuit comprises an NMOS transistor for transferring the voltage of the common node to the first sense node in response to a transmission signal.

7. The nonvolatile memory device of claim 1 , further comprising a data I/O circuit coupled to any one of the latches and configured to input or output data.

8. The nonvolatile memory device of claim 1 , wherein the set/reset circuit comprises a reset switch and a set switch which are coupled to each of the latches.

9. A method of operating a nonvolatile memory device, the method comprising:

providing a page buffer, comprising a sense circuit coupled between a first sense node and a second sense node, a transmission circuit coupled between the first sense node and a common node, a discharge switch configured to discharge the common node based on a voltage level of the second sense node, and a plurality of latches configured to transmit inputted data to the common node;

inputting data to any one of the latches;

transferring the data, inputted to the latch, to the common node;

transferring the data of the common node to the first sense node by deactivating the sense circuit and the discharge switch, and activating the transmission circuit; and

charging or discharging a selected bit line based on the data of the first sense node.

10. The method of claim 9 , wherein inputting the data to any one of the latches comprises:

inputting the data to a latch coupled to a data I/O circuit; and

transferring the data of the latch, coupled to the data I/O circuit, to another latch.

11. The method of claim 10 , wherein transferring the data of the latch, coupled to the data I/O circuit, to another latch comprises:

deactivating the discharge switch and transferring the data of the latch, coupled to the data I/O circuit, to the common node;

transferring the data of the common node to the first sense node by activating the transmission circuit;

transferring the data of the first sense node to the second sense node by deactivating the transmission circuit and activating the sense circuit;

discharging the common node or maintaining the common node in a previous state by operating the discharge switch based on the data of the second sense node; and

coupling the common node and a latch to which data will be inputted.