IP Library Granted Patent US 8,324,026
Granted Patent B2
US 8,324,026 · App. 13/190,922 · Granted Dec 4, 2012

Method for manufacturing a semiconductor component

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Quick Facts
Patent No.
US 8,324,026
App. No.
13/190,922
Granted
Dec 4, 2012
Kind
B2
Abstract

A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Claims (26)

1. A method for manufacturing a semiconductor component, comprising:

providing one or more electrical interconnect structures embedded in a mold compound, the one or more electrical interconnect structures having first and second major surfaces and a plurality of edges coupling the first major surface to the second major surface;

forming a dimple in a first portion of at least one of the one or more electrical interconnect structures;

exposing a portion of a first edge of the plurality of edges of at least one of the one or more electrical interconnect structures;

forming a first material over the exposed portion of the first edge;

separating the mold compound into at least two portions, and wherein providing the one or more electrical interconnect structures embedded in the mold compound further includes:

providing a leadframe having a tie bar with first and second leadframe leads extending from opposing sides of the tie bar; and

forming the dimple in the first portion of at least one of the one or more electrical interconnect structures includes forming the dimple on a first edge portion of the tie bar and exposing a portion of the first edge.

2. The method of claim 1 , wherein forming the dimple in the first portion of the at least one of the one or more electrical interconnect structures includes forming a protrusion extending from a second portion of at least one of the one or more electrical interconnect structures.

3. The method of claim 1 , wherein exposing the portion of the first edge of the plurality of edges of the at least one of the one or more electrical interconnect structures comprises sawing the one or more electrical interconnect structures.

4. The method of claim 1 , wherein exposing the portion of the first edge of the plurality of edges of the at least one of the one or more electrical interconnect structures comprises stamping the one or more electrical interconnect structures.

5. The method of claim 1 , wherein exposing the portion of the first edge of the plurality of edges of the at least one of the one or more electrical interconnect structures comprises etching the one or more electrical interconnect structures.

6. The method of claim 1 , wherein separating the mold compound into at least two portions includes sawing through the mold compound.

7. The method of claim 1 , wherein forming the first material over the exposed portion of the first edge comprises plating the first material over the exposed portion of the first edge.

8. The method of claim 1 , wherein forming the first material over the exposed portion of the first edge includes barrel plating the first material over the exposed portion of the first edge.

9. The method of claim 1 , wherein forming the first material over the exposed portion of the first edge comprises forming an electrically conductive material over the exposed portion of the first edge.

10. The method of claim 9 , wherein forming the first material over the exposed portion of the first edge further includes forming an anti-oxidizing coating over the electrically conductive material.

11. The method of claim 1 , wherein forming the dimple in the portion of the tie bar further includes forming a protrusion extending from another portion of the tie bar.

12. The method of claim 1 , wherein forming the dimple in the portion of the tie bar comprises stamping the portion of the tie bar.

13. A method for manufacturing a semiconductor component, comprising:

providing a leadframe having first and second major surfaces, a plurality of edges coupling the first major surface to the second major surface, a plurality of leadframe leads, and a tie bar with a first leadframe lead and a second leadframe lead extending from opposing sides of the tie bar;

forming a protrusion extending from a portion of the first major surface of the tie bar at a first edge thereof;

exposing a portion of the first edge of a plurality of edges of the tie bar from a mold compound; and

forming a first layer of conductive material over the exposed portion of the first edge.

14. The method of claim 13 , wherein forming the protrusion further includes forming a dimple in a portion of the second major surface of the tie bar.

15. The method of claim 13 , wherein forming the protrusion includes forming a plurality of protrusions extending from the first major surface of the tie bar.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →