Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
1. A method comprising:
determining a level of reliability of an area of a memory array in which a block of data is stored; and
storing error correction code associated with the block of data in one of the area of the memory array in which the block of data is stored or an area of the memory array near the area of memory array in which the block of data is stored in response to the level of reliability of the area of the memory array in which the block of data is stored being at least substantially equal to a desired level of reliability for the error correction code.
2. The method of claim 1 and further including:
storing the error correction code at a bit level that is less than a bit level at which the block of data is stored.
3. The method of claim 1 and further including determining if the level of reliability is at least substantially equal to the desired level of reliability if the error correction code is stored at a bit level that is less than a bit level at which the block of data is stored.
4. The method of claim 1 wherein determining the level of reliability comprises reading a table from memory comprising a calibrated reliability level for each of a plurality of areas of the memory array.
5. The method of claim 1 wherein determining the level of reliability comprises writing data, at a plurality of different bit levels, to each of a plurality of memory areas of the memory array.
6. A method comprising:
determining a plurality of levels of reliability, each with a corresponding bit level, for a plurality of cells of a memory array;
determining a desired level of reliability for the error correction code;
determining an area of the memory array having the reliability level of the plurality of reliability levels that is at least substantially equal to the desired reliability level; and
storing the error correction code to the area of the memory array using the corresponding bit level.
7. The method of claim 6 wherein generating the plurality of bit levels is accomplished at initial power-up of the memory device.
8. The method of claim 6 and further comprising linking the error correction code to the data block.
9. The method of claim 6 wherein determining the plurality of levels of reliability comprises:
storing a voltage to a cell;
storing a plurality of cells substantially adjacent to the cell;
reading a threshold voltage of the cell in response to the programming of the plurality of substantially adjacent cells; and
generating an indication of a level of reliability of the cell to remain at the first voltage.
10. A method comprising:
determining a desired level of reliability for received data that is error correction code;
determining a level of reliability for the data block at a bit level;
if the level of reliability for the data block is at least substantially equal to the desired level of reliability, writing the error correction code to the data block at the bit level;
if the level of reliability for the data block is less than the desired level of reliability, decreasing the bit level to a decreased bit level in order to increase the level of reliability to an increased level of reliability; and
if the increased level of reliability is at least substantially equal to the desired level of reliability, writing the correction code to the data block at the decreased bit level.
11. A device, comprising:
an array of memory cells; and
control circuitry coupled to the array of memory cells wherein the control circuitry is configured to program error correction code for a block of data by determining a desired level of reliability for the error correction code, determining a memory area level of reliability, at a bit level, for a memory area of the array of memory cells in which the block of data is stored, storing the error correction code with the block of data and at the bit level if the memory area level of reliability is at least substantially equal to the desired level of reliability, and storing the error correction code to another area of the array of memory cells if the memory area level of reliability is less than the desired level of reliability.
12. The device of claim 11 wherein the control circuitry is further configured to read analog data and to generate digital threshold voltage signals indicative of the read analog data.
13. The device of claim 11 wherein the control circuitry comprises circuitry to receive digital data indicative of a programmed memory state and to convert the digital data to an analog data signal indicative of a threshold voltage of the programmed memory state.
14. The device of claim 11 wherein the control circuitry is further configured to store a first threshold voltage to a first cell, program a plurality of cells substantially adjacent to the first cell with a second threshold voltage, read the first cell to determine an effect on the first threshold voltage by the second threshold voltage, and generate an indication of a reliability level of the first cell in response to the effect on the first threshold voltage.
15. The device of claim 11 wherein the device is a solid state memory device.