Three dimensional interconnect structure and method thereof
View Patent ↗A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
1. A three-dimensional interconnect structure, comprising:
a first substrate bonded to a second substrate, the first substrate comprising at least a device layer and a bulk semiconductor layer;
at least one metal pad disposed on the second substrate;
an electrically insulating layer disposed between the first and second substrates;
a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the at least one metal pad on the second substrate;
a dielectric coating on a sidewall of the via-hole;
a plasma-treated region of the at least one metal pad disposed on the second substrate; and
a via-metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the at least one metal pad of the second substrate.
2. A structure according to claim 1 , wherein the first and second substrates include microelectronic devices, microelectronic circuits, optical devices or MEMS devices.
3. A structure according to claim 1 , wherein the device layer includes microelectronic devices, microelectronic circuits, optical devices or MEMS devices.
4. A structure according to claim 1 , wherein the bulk semiconductor layer comprises a thinned substrate having a thickness less than 100 microns.
5. A structure according to claim 1 , wherein a surface of the metal pad on the second substrate comprises at least one of copper, tungsten, aluminum, titanium, titanium nitride, titanium-tungsten alloy, titanium-silicide, or a combination thereof.
6. A structure according to claim 1 , wherein the electrically insulating layer comprises at least one of an epoxy, an oxide, a polyimide, a benzocyclobutene, or a combination thereof.
7. A structure according to claim 1 , wherein the via-hole etched through the first substrate has an aspect ratio greater than 3:1.
8. A structure according to claim 1 , wherein the via-hole etched through the first substrate has a sidewall angle greater than 85 degrees.
9. A structure according to claim 1 , wherein the dielectric coating in the via comprises at least one of a parylene, a silicon oxide, and silicon nitride.
10. A structure according to claim 1 , wherein a diffusion barrier layer is located between the via-metal and the dielectric coating.
11. A structure according to claim 1 , wherein the via metal is copper, tungsten, polysilicon, or a combination thereof.
12. A structure according to claim 1 , wherein the device layer is apart from the semiconductor bulk layer.
13. A structure according to claim 1 , wherein the device layer is included in the semiconductor bulk layer.
14. A structure according to claim 1 , wherein the bulk semiconductor layer comprises at least a silicon layer, a silicon germanium layer, a III-V semiconductor material layer, a silicon carbide layer and a gallium nitride layer.
15. An electronics package comprising:
a first substrate having at least one refractory contact pad;
a second substrate bonded to the first substrate and including electronic devices;
a via extending through the second substrate to the contact pad of the first substrate
a via-fill metal disposed in the via and contacting the at least one contact pad; and
a plasma-treated refractory surface interface between the via-fill metal and the contact pad.
16. The package of claim 15 , wherein the plasma-treated refractory surface interface has a contact resistivity of less than 10 −6 Ω-cm.
17. The package of claim 15 , further comprising:
at least one metallization channel formed on an area of the second substrate and connecting the via-fill metal to at least one of the electronic devices.
18. The package of claim 15 , further comprising a third substrate bonded to the second substrate.
19. The package of claim 15 , further comprising a third substrate bonded to the first substrate adjacent the second substrate.
20. The package of claim 15 , wherein the contact pad comprises at least one of tungsten, aluminum, molybdenum, and silicide.
21. The package of claim 15 , wherein the via-fill metal comprises copper.
22. The package of claim 15 , wherein the first and second substrates are bonded together by at least one of an adhesive and a solder bonding.
23. The package of claim 15 , wherein the via has an aspect ratio of height to width ranging from 4:1 to 10:1.
24. An electronics package comprising:
a first substrate having at least one contact pad;
a second substrate bonded to the first substrate and including electronic devices;
a via having an aspect ratio of height to width ranging from 4:1 to 10:1, and extending through the second substrate to the contact pad of the first substrate
a via-fill metal disposed in the via and contacting the at least one contact pad; and
a plasma-treated surface interface between the via-fill metal and the contact pad.