Programming method for NAND flash memory device to reduce electrons in channels
View Patent ↗In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
1. A programming method for a NAND flash memory device comprising a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to a plurality of word lines, the programming method including a step of reducing electrons in channel, source and drain regions of the cell strings before a step of programming a memory cell to be programmed.
2. The method as claimed in claim 1 ,
wherein the step of reducing the electrons includes a step of biasing the word lines to be a voltage lower than a bias voltage of the P-well to accumulate holes at a channel surface to ionize interface traps which recombine with electrons during a self boosting operation upon programming for inhibit cells.
3. The method as claimed in claim 2 ,
wherein the step of reducing includes a step of negatively biasing the word lines against the P-well.
4. The method as claimed in claim 3 ,
wherein the step of negatively biasing includes step of applying a negative voltage to the word lines with the P-well grounded.
5. The method as claimed in claim 2 ,
wherein the step of reducing includes a step of positively biasing the P-well against the word lines.
6. The method as claimed in claim 5 ,
wherein the step of positively biasing includes a step of applying a positive voltage to the P-well with the word lines grounded.
7. The method as claimed in claim 5 ,
wherein the step of positively biasing includes a step of applying a positive voltage to the P-well while applying a negative voltage to the word lines.
8. A system for a NAND flash memory device comprising:
a NAND flash memory array which performs a step of reducing electrons in channel, source and drain regions of the cell strings before programming a memory cell to be programmed;
a peripheral circuitry which controls the step of reducing in the NAND flash memory array;
a control logic which controls an operation of the peripheral circuitry; and
a NAND controller which includes a buffer memory and manages an interface with an operation system in a unit of one sector of the NAND flash memory array.
9. The system as claimed in claim 8 ,
wherein the NAND controller controls data of the NAND flash memory array to be randomly programmed therein.
10. The system as claimed in claim 8 ,
wherein the buffer memory has a size of one sector of the NAND flash memory array.
11. The system as claimed in claim 8 ,
wherein NOP (Number of Operation for Programming in one page) of NAND flash memory array is equal to or larger than two.
12. The system according to claim 8 ,
wherein the NAND controller controls update data in a page of the NAND memory array to relocate to the same page without deleting old data.
13. The system according to claim 8 ,
wherein the NAND controller controls update data in a page of the NAND flash memory array to relocate to the same page, without deleting old data and erase operation within the same block.
14. The system according to claim 8 ,
wherein the NAND controller controls update data in a sector of a page of the NAND flash memory array to relocate to an empty sector within the same page with saving old data as an invalid data, without erase operation within the same block.