Semiconductor device and method of manufacturing the same
View Patent ↗In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center. A second wiring is then formed so as to be connected to the first wiring exposed in the window and extend onto the back surface of the semiconductor substrate over the step portions of the window except part of the step portions on the dicing line and near the dicing line, which extend perpendicular to the dicing line.
1. A semiconductor device comprising:
a support substrate having a dicing line;
a semiconductor die attached to the support substrate and having a first inclined surface, a second inclined surface and a third inclined surface, wherein;
each of the first, the second and the third inclined surfaces is disposed between a back surface and an end surface of the semiconductor die;
from a plan view, each of the first, the second and the third inclined surfaces has a length and a width;
from a plan view, each of the first and the second surfaces lies along a line that intersects the dicing line;
from a plan view, the third inclined surface is disposed between the first and the second inclined surfaces; and wherein the third inclined surface is perpendicular to at least one of the first and the second inclined surfaces;
a first wiring disposed at an elevation between the support substrate and the semiconductor die, wherein the first wiring is adjacent to the dicing line of the support substrate and the end surface of the semiconductor die; and
a second wiring electrically connected to the first wiring, wherein the second wiring, from a plan view:
the second wiring is fully disposed over the third inclined surface; and wherein
the second wiring is disposed over entire width of the first inclined surface along a first distance, as measured from the third inclined surface towards the dicing line, the first distance being less than the length of the first inclined surface; and
the second wiring is disposed over the entire width of the second inclined surface along a second distance, as measured from the third inclined surface towards the dicing line, the second distance being less than the length of the second inclined surface.
2. The semiconductor device of claim 1 , wherein the first inclined surface is parallel with the second inclined surface.
3. The semiconductor device of claim 1 , wherein the third inclined surface is perpendicular to the first inclined surface.
4. The semiconductor device of claim 1 , wherein the third inclined surface is perpendicular to the second inclined surface.
5. The semiconductor device of claim 1 , wherein the first, the second, and the third inclined surfaces each have a length, L, and a width, W, and wherein L>W.
6. The semiconductor device of claim 1 , wherein a recess is disposed between the first and the second inclined surfaces.
7. The semiconductor device of claim 6 , wherein the recess is wider at the back surface of the semiconductor die than at a front surface of the semiconductor die.
8. The semiconductor device of claim 1 , wherein, from a cross-sectional view, the second wiring extends continuously from the back surface of the semiconductor die adjacent to the first inclined surface to the back surface of the semiconductor die adjacent to the second inclined surface.
9. The semiconductor device of claim 8 , wherein, from a plan view, the second wiring extends beyond the widths of each of the first and second inclined surfaces.
10. The semiconductor device of claim 1 , further comprising an adhesive layer disposed between the semiconductor die and the support substrate.
11. A semiconductor device comprising: a support substrate having a dicing line; a semiconductor die attached to the support substrate, wherein the semiconductor die has:
a first inclined surface and a second inclined surface each disposed between a back surface and an end surface of the semiconductor die, each of the first and second inclined surfaces having a length and a width;
a third inclined surface disposed between the back surface and the end surface of the semiconductor die, wherein, in plan view, the third inclined surface is disposed between the first and the second inclined surfaces, and wherein the third inclined surface has a length and a width, and wherein the third inclined surface is perpendicular to at least one of the first and the second inclined surfaces;
a first wiring disposed at an elevation between the support substrate and the semiconductor die, wherein the first wiring is adjacent to the dicing line of the support substrate and the end surface of the semiconductor die; and
a second wiring electrically connected to the first wiring, wherein the second wiring, in plan view, is: disposed over the third inclined surface, disposed over the width of the first inclined surface along a first distance, as
measured from the third inclined surface towards the dicing line, the first
distance being less than the length of the first inclined surface, and
disposed over the width of the second inclined surface along a second distance, as measured from the third inclined surface towards the dicing line, the second distance being less than the length of the second inclined surface.
12. The semiconductor device of claim 11 , wherein, from a plan view, the lengths of each of the first, the second, and the third inclined surfaces is greater than the width thereof.
13. The semiconductor device of claim 11 , wherein, from a plan view, the second wiring extends beyond the widths of each of the first and second inclined surfaces.
14. The semiconductor device of claim 11 , wherein, from a plan view, the second wiring extends beyond the width of the third inclined surface.
15. The semiconductor device of claim 11 , wherein the first and second inclined surfaces extend along the semiconductor die in parallel orientation.