Semiconductor device
View Patent ↗In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.
1. A memory cell configured to operate as part of a semiconductor device, the memory comprising:
a first CMOS inverter comprising a first transistor of a P channel and a second transistor of an N channel;
a second CMOS inverter comprising a third transistor of a P channel and a fourth transistor of an N channel;
a first gate wiring connecting a gate of the first transistor and a gate of the second transistor;
a second gate wiring connecting a gate of the third transistor and a gate of the fourth transistor;
a first metal layer disposed on the first and second gate wirings and comprising a first wiring portion and a second wiring portion, the first wiring portion being connected to a drain of the first transistor, a drain of the second transistor and the second gate wiring, the second wiring portion being connected to a drain of the third transistor, a drain of the fourth transistor and the first gate wiring, the first wiring portion overlapping the second gate wiring at least partially, and the second wiring portion overlapping the first gate wiring at least partially;
a second metal layer disposed on the first metal layer; and
a third metal layer disposed on the second metal layer,
wherein the first transistor and the second transistor do not overlap in plan view of the memory cell, and the third transistor and the fourth transistor do not overlap in the plan view.
2. The semiconductor device of claim 1 , wherein the first wiring portion, the second gate wiring and the gate of the fourth transistor overlap, the second wiring portion, the first gate wiring and the gate of the first transistor overlap, and the second wiring portion, the first gate wiring and the gate of the second transistor also overlap.
3. The semiconductor device of claim 2 , wherein a width of the first wiring portion is equal to or smaller than a width of the second gate wiring at the gate of the fourth transistor, and a width of the second wiring portion is equal to or smaller than a width of the first gate wiring at the gates of the first and second transistors.
4. The semiconductor device of claim 1 , further comprising a first bit line, a second bit line, a first transfer gate and a second transfer gate, wherein the first bit line and the second bit line are part of the second metal layer, the first transfer gate is connected to the first bit line and the first CMOS inverter, and the second transfer gate is connected to the second bit line and the second CMOS inverter.
5. The semiconductor device of claim 1 , further comprising a power supply line and a ground line, wherein the power supply line and the ground line are part of the third metal layer.
6. The semiconductor device of claim 1 , further comprising a microcomputer that controls the memory cell, the memory cell and the microcomputer being disposed on a single substrate.
7. The semiconductor device of claim 6 , further comprising a flash memory, the flash memory being disposed on the single substrate and being controlled by the microcomputer.