Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics
View Patent ↗One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.
1. A method of standardized data creation and analysis of semiconductor technology node characteristics, comprising:
designing representative benchmark circuits for a clock path, a data path and a flip-flop path;
establishing at least one standard sensitization and measurement rule for delay and power for said representative benchmark circuits and across corners in said technology nodes;
performing, by employing a processor, a simulation by sweeping through a range of values and at predetermined intervals across said corners;
extracting data from said simulation;
writing said data to a databank; and
parsing and interpreting said data to produce at least one report.
2. The method as recited in claim 1 wherein each of said representative benchmark circuits includes variations in drive strength, gate loading and interconnect loading.
3. The method as recited in claim 1 wherein said sweeping occurs between slow and fast corners.
4. The method as recited in claim 1 wherein said sweeping occurs among various corners that define a safe zone.
5. The method as recited in claim 1 wherein said at least one report is selected from the group consisting of:
a 3D analysis and contour plot,
a 2D analysis, and
a tables formed of said data.
6. The method as recited in claim 1 wherein said technology node is selected from the group consisting of:
a scale of a process employed to fabricate an integrated circuit,
a substrate material employed in said integrated circuit,
an interconnect material employed in said integrated circuit, and
a device type employed in said integrated circuit.