IP Library Granted Patent US 8,889,511
Granted Patent B2
US 8,889,511 · App. 13/219,229 · Granted Nov 18, 2014

Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor

Inventors: Joseph A. Yedinak (Mountaintop, PA); Nathan L. Kraft (Pottsville, PA)
Assignee: Fairchild Semiconductor Corporation
H01L29/407H01L2924/01012H01L29/7811H01L29/7828H01L29/7805H01L2924/01019H02M3/33592H01L29/4933Y02B70/1475H01L2924/30105H01L29/0623H01L29/0661H01L29/66734H01L23/49816H01L29/7806H01L21/30655H01L29/7804H01L2221/68363H01L2224/16H01L29/402H01L29/42368H01L29/165H01L29/7396H01L29/495H01L2924/3025H01L21/3065H01L2924/10253H01L21/26586H01L29/7815H01L2924/13055H01L2924/19041H01L2924/13091H01L29/4236H01L29/0653H01L2924/15311H01L29/66348H01L2221/6834H01L29/0696H01L2924/1532H02M3/00H01L29/41766H02M7/48H01L29/0634H01L2924/01078H01L29/4238H01L23/4952H01L29/7813H01L21/6835H01L2924/3011H01L29/1095H01L29/7831H01L21/31116H01L29/7802
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Quick Facts
Patent No.
US 8,889,511
App. No.
13/219,229
Granted
Nov 18, 2014
Kind
B2
Abstract

In one general aspect, a method can include forming a shield dielectric layer in a trench in a semiconductor substrate, forming a shield electrode on at least a portion of the shield dielectric layer, and etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench. The method can include forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench, forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer, and forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer.

Claims (50)

1. A method of manufacturing a semiconductor device comprising:

forming a shield dielectric layer in a trench in a semiconductor substrate;

forming a shield electrode on at least a portion of the shield dielectric layer;

etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench;

forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench;

forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer;

forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer such that the shield electrode has a first portion disposed lower in the trench than a bottom portion of the second conductive gate electrode and such that the shield electrode has a second portion disposed higher in the trench than a top portion of the second conductive gate electrode;

forming a source contact in contact with the second portion of the shield electrode;

forming a well region in contact with the first sidewall of the trench;

forming a source region in contact with the first sidewall of the trench and inside the well region; and

forming an electrical contact between the shield electrode and the well region inside a mesa via a body trench adjacent to the trench.

2. The method of claim 1 , wherein the forming the well region is performed with a p-well implant.

3. The method of claim 1 , wherein the forming the source region is performed with an n+ source implant.

4. The method of claim 1 , further comprising depositing a layer of borophosphosilicate glass (BPSG).

5. The method of claim 1 , further comprising performing a contact etch and a p+ heavy body implant.

6. The method of claim 1 , further comprising metallizing at least one surface to form the source contact.

7. The method of claim 1 , wherein the gate dielectric layer forms a trough on each side of the shield electrode inside the trench.

8. A method, comprising:

forming a trench having a first trench sidewall and a second trench sidewall;

forming a shield dielectric layer on the first trench sidewall, a bottom surface of the trench, and the second trench sidewall;

forming a conductive shield electrode having a bottom portion disposed on the shield dielectric layer and having a top portion;

forming a gate dielectric layer on at least a portion of the shield dielectric layer;

forming a first conductive gate electrode on a first side of the conductive shield electrode and insulated from the first trench sidewall by the gate dielectric layer;

forming a second conductive gate electrode on a second side of the conductive shield electrode and insulated from the second trench sidewall by the gate dielectric layer;

forming a source metal in contact with the top portion of the conductive shield electrode, the conductive shield electrode extending vertically from the bottom portion disposed on the shield dielectric layer to the top portion in contact with the source metal, the source metal being insulated from first conductive gate electrode and insulated from the second conductive gate electrode;

forming a well region in contact with the first trench sidewall;

forming a source region in contact with the first trench sidewall and inside the well region; and

forming an electrical contact between the conductive shield electrode and the well region inside a mesa via a body trench adjacent to the trench.

9. The method of claim 8 , wherein the bottom portion of the conductive shield electrode extends deeper into the trench than bottom portion of the first conductive gate electrode and the top portion of the conductive shield electrode is disposed higher in the trench than a top portion of the first conductive gate electrode.

10. The method of claim 8 , wherein the conductive shield electrode is disposed between the first conductive gate electrode and the second conductive gate electrode.

11. The method of claim 8 , further comprising:

forming a drift region of a first conductivity type, the forming the well region including forming the well region above the drift region, the well region having a second conductivity type opposite the first conductivity type, at least a portion of the trench being disposed in the well region and being disposed in the drift region.

12. The method of claim 8 , further comprising:

forming a body trench extending deeper into the well region than the source region.

13. A method, comprising:

forming a trench having a first trench sidewall and a second trench sidewall;

forming a first conductive gate electrode disposed along and insulated from the first trench sidewall;

forming a second conductive gate electrode disposed along and insulated from the second trench sidewall;

forming a conductive shield electrode disposed between the first conductive electrode and the second conductive gate electrode, the conductive shield electrode having a first portion extending deeper into the trench than the first conductive gate electrode, the conductive shield electrode having a second portion disposed higher in the trench than the first conductive gate electrode and disposed vertically above the first portion of the conductive shield electrode, the second portion being in contact with a source metal;

forming a well region in contact with the first trench sidewall;

forming a source region in contact with the first trench sidewall and inside the well region; and

forming an electrical contact between the conductive shield electrode and the well region inside a mesa via a body trench adjacent to the trench.

14. The method of claim 13 , wherein the first portion of the conductive shield electrode extends deeper into the trench than a bottom portion of the first conductive gate electrode.

15. The method of claim 13 , wherein the second portion of the conductive shield electrode is disposed higher in the trench than a top portion of the first conductive gate electrode.

16. The method of claim 13 , further comprising:

forming a drift region of a first conductivity type; and

forming the well region above the drift region, the well region having a second conductivity type opposite the first conductivity type, at least a portion of the trench being disposed in the well region and being disposed in the drift region.

17. The method of claim 1 , wherein the semiconductor substrate includes silicon carbide.

18. The method of claim 8 , wherein the forming the trench includes forming the trench in silicon carbide.

19. The method of claim 13 , wherein the forming the trench includes forming the trench in silicon carbide.

Assignments (8)
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2014
From: CHALLA, ASHOK; ELBANHAWY, ALAN; GREBS, THOMAS E.; KRAFT, NATHAN L.; PROBST, DEAN E.; RIDLEY, RODNEY S.; SAPP, STEVEN P.; WANG, QI; YUN, CHONGMAN; LEE, J.G.; WILSON, PETER H.; YEDINAK, JOSEPH A.; JUNG, J.Y.; JANG, H.C.; SANI, BABAK S.; STOKES, RICHARD; DOLNY, GARY M.; MYTYCH, JOHN; LOSEE, BECKY; SELSLEY, ADAM; HERRICK, ROBERT; MURPHY, JAMES J.; MADSON, GORDON K.; MARCHANT, BRUCE D.; REXER, CHRISTOPHER L.; KOCON, CHRISTOPHER B.; WOOLSEY, DEBRA S
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 033833/0697 →
Continuity (6)
Division 11963668 · Dec 21, 2007
Continuation 11026276 · Dec 29, 2004
Continuation In Part 10640742 · Aug 14, 2003
Continuation In Part 10442670 · May 20, 2003
Provisional Application 60533790 · Dec 30, 2003
Related Publication 20110312138A1 · Dec 22, 2011