Semiconductor memory apparatus having a pre-discharging function, semiconductor integrated circuit having the same, and method for driving the same

1. A semiconductor memory apparatus comprising:

a bit line coupled to a plurality of memory cells;

a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated; and

a bit line discharge block coupled to the bit line and configured to discharge the bit line when the bit line discharge signal is enabled,

wherein the discharge controller enables the bit line discharge signal in response to a bit line discharge enable signal when an active mode signal is enabled, and enables the bit line discharge signal in response to a first signal when the active mode signal is disabled,

wherein the discharge controller comprises:

a first logic circuit unit configured to receive an active mode signal and a bit line discharge enable signal, and output a low level signal when each of the active mode signal and the bit line discharge enable signal is at a high level;

a second logic circuit unit configured to receive an active mode bar signal and a first signal, and output a low level signal when each of the active mode bar signal and the first signal is at a high level; and

a third logic circuit unit configured to receive output signals of the first and second logic circuit units.

2. The semiconductor memory apparatus according to claim 1 , wherein the discharge controller is configured to receive the active mode signal, the bit line discharge enable signal, and the first signal, and drive the bit line discharge block, when the first signal is enabled even though the active mode signal is disabled.

3. The semiconductor memory apparatus according to claim 2 , wherein the discharge controller is configured to enable the active mode signal and the bit line discharge enable signal at the same time.

4. The semiconductor memory apparatus according to claim 2 , wherein a pre-discharge period of the bit line is decided by an enable period of the first signal.

5. The semiconductor memory apparatus according to claim 1 , wherein the bit line discharge block comprises a dummy switching element electrically coupled to the bit line and a bit line discharge signal line.

6. A semiconductor memory apparatus comprising:

a cell array region comprising a plurality of word lines, a plurality of bit lines arranged to cross the respective word lines, and a plurality of memory cells selectively coupled to the word lines and the bit lines;

a bit line discharge block comprising a plurality of dummy cells coupled to the respective bit lines and configured to discharge the bit lines in response to a bit line discharge signal; and

a discharge controller configured to provide enabled the bit line discharge signal when an active mode signal is enabled and provide an additional enabled bit line discharge signal to pre-discharge the bit lines by a predetermined amount, before an enabled active mode signal is applied to the cell array region,

wherein the discharge controller is configured to receive the active mode signal, a bit line discharge enable signal, and a first signal, and drive the bit line discharge block, when the first signal is enabled even though the active mode signal is disabled,

wherein the discharge controller is configured to enable the active mode signal and the bit line discharge enable signal at the same time,

wherein the discharge controller comprises:

a first logic circuit unit configured to receive the active mode signal and the bit line discharge enable signal, and output a low level signal when each of the active mode signal and the bit line discharge enable signal is at a high level;

a second logic circuit unit configured to receive an active mode bar signal and the first signal, and output a low level signal when each of the active mode bar signal and the first signal is at a high level; and

a third logic circuit unit configured to receive output signals of the first and second logic circuit units.

7. The semiconductor memory apparatus according to claim 6 , wherein a pre-discharge period of the bit lines is decided by an enable period of the first signal.

8. The semiconductor memory apparatus according to claim 6 , wherein the bit line discharge block comprises dummy switching elements electrically coupled to the bit lines and a bit line discharge signal line.

9. A semiconductor integrated circuit comprising:

a signal transmission line;

a discharge block coupled to the signal transmission line, and configured to discharge data of the signal transmission line in response to a discharge signal; and

a control block coupled to the discharge block, and configured to provide the discharge signal which is enabled at regular discharge timing and pre-discharge timing before the regular discharge timing, respectively,

wherein the regular discharge timing is decided when an active mode signal is enabled and the pre-discharge timing is decided when the active mode signal is disabled,

wherein the pre-discharge timing is decided by a first signal having a predetermined enable period before the active mode signal,

wherein the control block comprises:

a first logic circuit unit configured to receive the active mode signal and a discharge enable signal, and output a low level signal when each of the active mode signal and the discharge enable signal is at a high level;

a second logic circuit unit configured to receive an active mode bar signal and the first signal and output a low level signal when each of the active mode bar signal and the first signal is at a high level; and

a third logic circuit unit configured to receive output signals of the first and second logic circuit units.