Semiconductor chip having staggered arrangement of bonding pads
A semiconductor integrated circuit device includes a semiconductor chip including input/output cells, pads formed on a surface of the semiconductor chip, and interconnects formed on the surface of the semiconductor chip to electrically connect at least some of the plurality of input/output cells and at least some of the plurality of pads. A first plurality of the pads located in a center portion of the semiconductor chip are arranged in a rectangular dot grid pattern, and a second plurality of the pads located in at least one of four corner portions of the semiconductor chip are arranged in a staggered dot pattern.
1. A semiconductor integrated circuit device comprising:
a semiconductor chip including input/output cells;
pads formed on a surface of the semiconductor chip; and
interconnects formed on the surface of the semiconductor chip to electrically connect one or more of the input/output cells and one or more of the pads, wherein
a first plurality of the pads located in a center portion of the semiconductor chip are arranged in a rectangular dot grid pattern,
a second plurality of the pads located in two corner portions which are disposed in a same side of the semiconductor chip are arranged in a staggered dot pattern, and
a third plurality of the pads located between the two corner portions are arranged in the rectangular dot grid pattern.
2. The semiconductor integrated circuit device of claim 1 , wherein
each of the pads arranged in the rectangular dot grid pattern is in the shape of a rectangle when viewed in plan, and each of the pads arranged in the staggered dot pattern is in the shape of a rectangle which is tilted at an angle of 45° relative to the rectangular shape of the pads arranged in the rectangular dot grid pattern when viewed in plan.
3. The semiconductor integrated circuit device of claim 1 , wherein
a surface metal layer of each of the plurality of pads is in the shape of a rectangle when viewed in plan, and
a lower metal layer below the surface metal layer of each of the pads arranged in the staggered dot pattern is in the shape of a rectangle which is tilted at an angle of 45° relative to the rectangular shape of the surface metal layer when viewed in plan.
4. The semiconductor integrated circuit device of claim 1 , wherein
the pads arranged in the rectangular dot grid pattern are power supply terminals, and the pads arranged in the staggered dot pattern are signal terminals.
5. The semiconductor integrated circuit device of claim 1 , wherein
pads are not provided in a pad forming region or a region around the pad forming region of a designated area where density of the interconnects is high.
6. The semiconductor integrated circuit device of claim 1 , wherein
pads are not provided in a pad forming region or a region around the pad forming region of a designated area where an analog element is present.
7. The semiconductor integrated circuit device of claim 1 , wherein
one or more rows of the pads closest to an outer perimeter of the semiconductor chip are power supply terminals.
8. The semiconductor integrated circuit device of claim 1 , wherein
an interconnect connecting one of the input/output cells with one of the second plurality of pads intersects the perimeter of the chip at an angle consistent with the staggered dot pattern.
9. The semiconductor integrated circuit device of claim 1 , wherein
the interconnect connecting one of the input/output cells with one of the second plurality of pads intersects the one of the second plurality of pads at an angle of substantially 90 degrees.
10. The semiconductor integrated circuit device of claim 1 , wherein
a distance between adjacent two of the second plurality of pads arranged in the staggered pattern is longer than a distance between adjacent two of the first plurality of pads arranged in the rectangular dot grid pattern.
11. The semiconductor integrated circuit device of claim 1 , wherein
the second plurality of pads arranged in the staggered pattern includes at least three pads.
12. The semiconductor integrated circuit device of claim 1 , wherein the input/output cells are located on a peripheral area outside the second plurality of pads and the third plurality of the pads.
13. A semiconductor integrated circuit device comprising:
a semiconductor chip including a plurality of input/output cells;
a plurality of pads formed on a surface of the semiconductor chip; and
interconnects formed on the surface of the semiconductor chip to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads, wherein
a first group of the plurality of pads are located in a center portion of the semiconductor chip and arranged in a first pattern,
a second group of the plurality of pads are located in two corner portions which are disposed in a same side of the semiconductor chip and arranged in a second pattern, an angle of the second pattern is offset from an angle of the first pattern by an acute angle greater than 0 degrees, and
a third group of the plurality of pads are located between the two corner portions and arranged in the first pattern.
14. The semiconductor integrated circuit device of claim 13 , wherein
an interconnect connecting one of the input/output cells with one of the second plurality of pads intersects the perimeter of the chip at an angle consistent with an angle of the second pattern.
15. The semiconductor integrated circuit device of claim 13 , wherein
the interconnect connecting one of the input/output cells with one of the second plurality of pads intersects the one of the second plurality of pads at an angle of substantially 90 degrees.
16. A semiconductor integrated circuit device comprising:
a semiconductor chip including a plurality of input/output cells;
a plurality of pads formed on a surface of the semiconductor chip; and
interconnects formed on the surface of the semiconductor chip to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads, wherein
a first group of the plurality of pads located in a cross-shaped center portion of the semiconductor chip extending to outer edges of a pad region of the semiconductor chip, the first group of the plurality of pads arranged in a first pattern,
a second group of the plurality of pads located in at least two corner portions on the same side of the pad region of the semiconductor chip, the second group of the plurality of pads arranged in a second pattern, an angle of the second pattern is offset from an angle of the first pattern by an acute angle greater than 0 degrees, and
the second group of the plurality of pads bound on two sides by the first group of the plurality of pads.