Electrostatic discharge (ESD) tolerance for a lateral double diffusion metal oxide semiconductor (LDMOS) transistor
View Patent ↗An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.
1. A semiconductor transistor comprising:
a semiconductor layer of a first general conductivity type;
a drift layer of the first general conductivity type formed in a surface portion of the semiconductor layer;
a drain layer of the first general conductivity type formed in a surface portion of the drift layer;
a base layer of a second general conductivity type formed in a surface portion of the semiconductor layer apart from the drift layer;
a source layer of the first general conductivity type formed in a surface portion of the base layer and comprising a plurality of openings;
a contact layer of the second general conductivity type filling each of the openings in the source layer so that there is a distance between an edge of the contact layer and a corresponding edge of the source layer;
a gate insulation film covering at least part of the base layer and part of the semiconductor layer;
a gate electrode disposed on the gate insulation film; and
another semiconductor layer of the second general conductivity type contiguous to the contact layer and extending from the edge of the contact layer into the base layer under the source layer around the opening, wherein an extended portion of the another semiconductor layer is connected with another extended portion of the another semiconductor layer extending from an edge of another contact layer.
2. The semiconductor device of claim 1 , wherein the openings are disposed at a regular interval.
3. The semiconductor device of claim 1 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is a distance at which the ESD tolerance of the transistor starts to be saturated.
4. The semiconductor device of claim 3 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is at least about 1.5 μm.
5. The semiconductor device of claim 1 , wherein the first general conductivity type is a N-type conductivity and the second general conductivity type is a P-type conductivity.
6. The semiconductor device of claim 1 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is configured so that an ESD tolerance of the transistor as a function of the distance is saturated.
7. The semiconductor device of claim 6 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is about 1.5 μm.
8. The semiconductor device of claim 1 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is at least about 1.5 μm.
9. The semiconductor device of claim 1 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is about 1.5 μm.
10. The semiconductor device of claim 1 , wherein the distance between the edge of the contact layer and the corresponding edge of the source layer is about 1.5 μm to about 2.6 μm.
11. The semiconductor device of claim 10 , wherein the first general conductivity type is an N-type conductivity, and the second general conductivity type is a P-type conductivity.
12. The semiconductor device of claim 1 , further comprising an interlayer insulation film that covers the gate electrode and at least a portion of the source layer.
13. The semiconductor device of claim 12 , wherein the interlayer insulation film comprises a contact groove formed over the openings in the source layer.
14. The semiconductor device of claim 13 , wherein a width of the contact groove is about the same as a width of the openings in the source layer.
15. The semiconductor device of claim 13 , wherein a width of the contact groove is greater than a width of the openings in the source layer.
16. The semiconductor device of claim 13 , wherein a width of the contact groove is about the same as a width of the another semiconductor layer.
17. The semiconductor device of claim 13 , wherein the interlayer insulation film comprises a second contact groove formed over the drain layer.