Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.
1. A method for manufacturing a semiconductor device comprising:
forming a first recess over a semiconductor substrate;
forming a first insulation film over the first recess and the semiconductor substrate;
forming a plurality of second recesses under the first recess by etching the first insulation film and the semiconductor substrate;
forming a second insulation film over the second recesses and the first insulation film;
forming gate patterns over the second insulation film, wherein the gate patterns each fill in the second recesses and extend upwards while having a substantially uniform width; and
forming a second insulation film pattern and a first insulation film pattern located at the surface of the substrate at a first edge and at a second edge of each of the gate patterns by etching the second and the first insulation films until the semiconductor substrate is exposed,
wherein a sum of a thickness of the second and a thickness of the first insulation film patterns is different from each other at the first edge and at the second edge.
2. The method according to claim 1 , wherein the first recess is formed to have a depth of 100 Ř400 Å.
3. The method according to claim 1 , wherein the first insulation film includes an oxide film and is formed to have a thickness of 10 Ř100 Å.
4. The method according to claim 1 , wherein the second recesses are formed to have a depth of 1200 Ř1500 Å.
5. The method according to claim 1 , wherein the second insulation film includes an oxide film and is formed to have a thickness of 10 Ř100 Å.
6. The method according to claim 1 , wherein a width of the first recess is greater than the width of the second recesses.
7. The method according to claim 1 , wherein the semiconductor substrate coupled to a storage node contact plug is formed to be at a higher level than the semiconductor substrate coupled to a bit line contact plug.
8. The method according to claim 1 , wherein the forming of the gate patterns includes:
sequentially forming a polysilicon film, a metal silicide, and an oxide film over the second insulation film; and
etching the polysilicon film, the metal silicide, and the oxide film using a gate pattern mask until the second insulation film is exposed.
9. The method according to claim 1 , after the forming of the gate patterns, the method further comprising:
forming third and fourth insulation films over the gate patterns; and
etching the third and fourth insulation films until the semiconductor substrate is exposed.