Memory device and method for operating the same
View Patent ↗A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.
1. A memory comprising:
first flag cells configured to store first flag data;
second flag cells configured to store second flag data;
third flag cells configured to store third flag data;
first sensing nodes having voltage levels determined by the first flag data of the first flag cells, respectively;
second sensing nodes having voltage levels determined by the second flag data of the second flag cells, respectively;
third sensing nodes having voltage levels determined by the third flag data of the third flag cells, respectively;
a selection circuit configured to select the first sensing nodes or the second sensing nodes in response to a flag address; and
a determination circuit having a first internal node through which current corresponding to voltage levels of the selected sensing nodes flows and a second internal node through which current corresponding to the voltage levels of the third sensing nodes flows, wherein the determination circuit is configured to determine a logic value of flag data corresponding to the selected sensing nodes among the first and second flag data by using the amount of current flowing through the first internal node and determine a logic value of the third flag data by using the amount of current flowing through the second internal node.
2. The memory of claim 1 , wherein the selection circuit discharges sensing nodes other than the selected sensing node among the first sensing nodes and the second sensing nodes.
3. The memory of claim 1 , wherein the determination circuit is configured to determine the logic value of the flag data corresponding to the sensing nodes by comparing the amount of current flowing through the first internal node with a reference current amount and determine the logic value of the third flag data by comparing the amount of current flowing through the second internal node with the reference current amount.
4. The memory of claim 1 , further comprising:
first page buffers configured to determine the respective voltage levels of first sensing nodes in response to the first flag data of the first flag cells, respectively;
second page buffers configured to determine the respective voltage levels of second sensing nodes in response to the second flag data of the second flag cells, respectively; and
third page buffers configured to determine the respective voltage levels of third sensing nodes in response to the third flag data of the third flag cells, respectively.