METHODS AND APPARATUS FOR INCLUDING AN AIR GAP IN CARBON-BASED MEMORY DEVICES
In some aspects, a reversible resistance-switching metal-insulator-metal stack is provided that includes a first conducting layer, a carbon nano-tube (“CNT”) material above the first conducting layer, a second conducting layer above the CNT material, and an air gap between the first conducting layer and the CNT material. Numerous other aspects are provided.
1 . A reversible resistance-switching metal-insulator-metal (“MIM”) stack comprising:
a first conducting layer;
a carbon nano-tube (“CNT”) material above the first conducting layer;
a second conducting layer above the CNT material; and
an air gap between the first conducting layer and the CNT material.
2 . The reversible resistance-switching MIM stack of claim 1 , further comprising a dielectric material between the first conducting layer and the CNT material.
3 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material comprises the air gap.
4 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material comprises one or more of a porous dielectric film, a spin-coated dielectric nano-structure, and a shrunken dielectric layer.
5 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material comprises one or more pores, holes or openings.
6 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material comprises one or more of aluminum oxide (“Al 2 O 3 ”), boron nitride (“BN”), silicon dioxide (“SiO 2 ”), silicon nitride (“Si 3 N 4 ”), hafnium oxide (“HfO 2 ”), tantalum oxide (“Ta 2 O 5 ”), tungsten oxide (“WO 3 ”), molybdenum trioxide (“MoO 3 ”), zinc oxide (“ZnO”), titanium oxide (“TiO 2 ”), and zirconium oxide (“ZrO 2 ”).
7 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material has a thickness between about 2 nm to about 10 nm.
8 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material comprises one or more of single-walled, double-walled, and multi-walled dielectric nanotubes.
9 . The reversible resistance-switching MIM stack of claim 2 , wherein the dielectric material comprises dielectric nano-wires.
10 . The reversible resistance-switching MIM stack of claim 1 , wherein the air gap has a diameter of about 10 nm or less.
11 . A carbon nano-tube (“CNT”) memory cell comprising:
a first conductor;
a steering element above the first conductor;
a first conducting layer above the first conductor;
a CNT material above the first conducting layer;
a second conducting layer above the CNT material; and
an air gap between the first conducting layer and the CNT material.
12 . The CNT memory cell of claim 11 , further comprising a dielectric material between the first conducting layer and the CNT material.
13 . The CNT memory cell of claim 12 , wherein the dielectric material comprises the air gap.
14 . The CNT memory cell of claim 12 , wherein the dielectric material comprises one or more of a porous dielectric film, a spin-coated dielectric nano-structure, and a shrunken dielectric layer.
15 . The CNT memory cell of claim 12 , wherein the dielectric material comprises one or more pores, holes or openings.
16 . The CNT memory cell of claim 12 , wherein the dielectric material comprises one or more of aluminum oxide (“Al 2 O 3 ”), boron nitride (“BN”), silicon dioxide (“SiO 2 ”), silicon nitride (“Si 3 N 4 ”), hafnium oxide (“HfO 2 ”), tantalum oxide (“Ta 2 O 5 ”), tungsten oxide (“WO 3 ”), molybdenum trioxide (“MoO 3 ”), zinc oxide (“ZnO”), titanium oxide (“TiO 2 ”), and zirconium oxide (“ZrO 2 ”).
17 . The CNT memory cell of claim 12 , wherein the dielectric material has a thickness between about 2 nm to about 10 nm.
18 . The CNT memory cell of claim 12 , wherein the dielectric material comprises one or more of single-walled, double-walled, and multi-walled dielectric nanotubes.
19 . The CNT memory cell of claim 12 , wherein the dielectric material comprises dielectric nano-wires.
20 . The CNT memory cell of claim 11 , wherein the air gap has a diameter of about 10 nm or less.
21 . A method of forming a carbon nano-tube (“CNT”) memory cell, the method comprising:
forming a first conductor;
forming a steering element above the first conductor;
forming a first conducting layer above the first conductor;
forming a CNT material above the first conducting layer;
forming a second conducting layer above the CNT material; and
forming an air gap between the first conducting layer and the CNT material.
22 . The method of claim 21 , further comprising forming a dielectric material between the first conducting layer and the CNT material.
23 . The method of claim 22 , wherein the dielectric material comprises the air gap.
24 . The method of claim 22 , wherein the dielectric material comprises one or more of a porous dielectric film, a spin-coated dielectric nano-structure, and a shrunken dielectric layer.
25 . The method of claim 22 , wherein the dielectric material comprises one or more pores, holes or openings.
26 . The method of claim 22 , wherein the dielectric material comprises one or more of aluminum oxide (“Al 2 O 3 ”), boron nitride (“BN”), silicon dioxide (“SiO 2 ”), silicon nitride (“Si 3 N 4 ”), hafnium oxide (“HfO 2 ”), tantalum oxide (“Ta 2 O 5 ”), tungsten oxide (“WO 3 ”), molybdenum trioxide (“MoO 3 ”), zinc oxide (“ZnO”), titanium oxide (“TiO 2 ”), and zirconium oxide (“ZrO 2 ”).
27 . The method of claim 22 , wherein the dielectric material has a thickness between about 2 nm to about 10 nm.
28 . The method of claim 22 , wherein the dielectric material comprises one or more of single-walled, double-walled, and multi-walled dielectric nanotubes.
29 . The method of claim 22 , wherein the dielectric material comprises dielectric nano-wires.
30 . The method of claim 21 , wherein the air gap has a diameter of about 10 nm or less.