Semiconductor memory apparatus
View Patent ↗A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering to an external data in accordance with the second external reference voltage.
1. A semiconductor memory apparatus comprising:
a clock cycle detecting unit configured to enable a detection signal when a cycle of a clock signal is shorter than a predetermined cycle;
a voltage selecting unit configured to selectively output a first voltage and a second voltage as a selection voltage in response to the detection signal;
a first internal circuit configured to receive the first voltage; and
a second internal circuit configured to receive the selection voltage.
2. The semiconductor memory apparatus according to claim 1 , wherein the first voltage and the second voltage are at a same voltage level, but are outputted from different power sources.
3. The semiconductor memory apparatus according to claim 2 , wherein the clock cycle detecting unit includes:
a pulse generating unit configured to generate a pulse that is enabled for a predetermined time, when a power-up signal is enabled;
a counting unit configured to generate a counting signal by counting the clock signal for an enable section of the pulse; and
a detection signal generating unit configured to enable the detection signal when a counted value of the counting signal is more than a predetermined value.
4. The semiconductor memory apparatus according to claim 3 , wherein the counting unit initializes the counting signal in response to the power-up signal.
5. The semiconductor memory apparatus according to claim 3 , the detection signal generating unit includes:
a decoder configured to enable a decoding signal when a predetermined decoding value is the same as a decoding value of the counting signal; and
a latch unit configured to latch the enabled decoding signal and then output the decoding signal as the detection signal.
6. The semiconductor memory apparatus according to claim 5 , wherein the latch unit initializes the detection signal in response to the power-up signal.