Digital device interconnect interface and system
View Patent ↗A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.
1. An interconnect bus comprising:
a first bus line configured to carry a clock signal; and
a second bus line configured to carry data formatted according to a specified bus protocol;
wherein during a first mode of operation:
the clock signal is transmitted over the first bus line source synchronously with the data transmitted over the second bus line; and
the data is sampled on at least one of a rising edge and a falling edge of the clock signal at respective receiving ends of the first bus line and the second bus line; and
wherein during a second mode of operation:
the clock signal is not transmitted over the first bus line;
the data is not transmitted over the second bus line; and
the first bus line and the second bus line are driven with static states corresponding to command/control state information of the specified bus protocol, to provide the command/control state information at the respective receiving ends of the first bus line and the second bus line.
2. The interconnect bus of claim 1 , wherein the command/control state information comprises:
USB (Universal Serial Bus) Idle state;
USB Attach/Resume state;
USB Suspend state; and
and USB Reset state.
3. The interconnect bus of claim 2 ;
wherein during the second mode of operation:
when providing the USB Idle state, the first bus line is driven to a first logic value and the second bus line is driven to a second logic value, for a specified number of clock periods;
when providing the USB Attach/Resume state, the first bus line is driven to the second logic value and the second bus line is driven to the first logic value, during a first time period;
when providing the USB Suspend state, the first bus line is driven to the first logic value and the second bus line is driven to the second logic value, during a second time period; and
when providing the USB Reset state, the first bus line is driven to the second logic value and the second bus line is driven to the second logic value, during a third time period.
4. The interconnect bus of claim 3 , wherein the specified number of clock periods, the first time period, the second time period, and the third time period satisfy USB specification requirements.
5. The interconnect bus of claim 1 , wherein the interface is configured to couple USB (Universal Serial Bus) devices without using a physical layer (PHY) and/or USB cables.
6. The interconnect bus of claim 1 , wherein the data is sampled on the rising edge of the clock signal and on the falling edge of the clock signal.
7. A system comprising:
a first device and a second device both configured to transmit and receive data according to a specified bus protocol;
an interconnect bus comprising two signal lines coupling the first device and the second device, wherein one of the two signal lines is a bidirectional clock line and a remaining one of the two signal lines is a bidirectional data line;
wherein the interconnect bus has at least a first operating mode and a second operating mode;
wherein in the first operating mode the interconnect bus is configured to transmit data between the first device and the second device over the bidirectional data line, and a clock signal source synchronously with the data between the first device and the second device over the bidirectional clock line;
wherein in the second operating mode:
the data and the clock signal are not transmitted; and
one of the first device and the second device is configured to drive static states on the bidirectional clock line and the bidirectional data line, wherein respective combinations of the driven static states convey command/control state information associated with the specified bus protocol to a remaining one of the first device and the second device.
8. The system of claim 7 , wherein the first device is configured to apply weak pull-up/pull-down to maintain an idle state on the interconnect bus when no active data transfer takes place on the bidirectional data line.
9. The system of claim 8 , wherein the first device is configured to temporarily remove the weak pull-up/pull-down when it is receiving and/or transmitting data on the bidirectional data line.
10. The system of claim 7 , wherein the data transmitted over the bidirectional data line is sampled at a rising edge and at a falling edge of the clock signal transmitted over the bidirectional clock line.
11. The system of claim 7 , wherein the first device and the second device are each configured to:
send and/or receive data over the bidirectional data line; and
send the clock signal over the bidirectional clock line source synchronously with the data being sent over the bidirectional data line.
12. The system of claim 7 , wherein the interconnect bus further comprises a plurality of additional bidirectional data lines.
13. A device comprising:
a bus interface configured to couple to a first interconnect line and a second interconnect line, to transmit and/or receive data conforming to a specified bus protocol over the first interconnect line, and to transmit and/or receive a clock signal over the second interconnect line; and
control circuitry configured to:
transmit the clock signal source synchronously with the data through the bus interface when transmitting data through the bus interface; and
when not transmitting and not receiving the clock signal and the data through the bus interface, conveying command/control state information of the specified bus protocol through the bus interface by driving static states on the first interconnect line and the second interconnect line through the bus interface, wherein each respective combination of the driven static states corresponds to information indicative of a respective command/control state of the specified bus protocol.
14. The device of claim 13 , wherein the control circuitry is further configured to:
sample the data received through the bus interface on at least on a rising edge of the clock signal received over the bus interface.
15. The device of claim 13 , wherein the control circuitry is configured to transmit data over the bus interface according to the specified bus protocol, wherein the specified bus protocol is configured with a handshake mechanism to intrinsically prevent bus contention.
16. The device of claim 13 , wherein the control circuitry is configured to drive the static states on the first interconnect line and the second interconnect line through the bus interface for respective specified time periods when conveying command/control state information of the specified bus protocol through the bus interface.
17. A method comprising:
during a first mode of operation:
transmitting data onto a first signal line according to a specified bus protocol; and
transmitting, source-synchronously with the data, a clock signal onto a second signal line; and
during a second mode of operation:
instead of transmitting the data and the clock signal, conveying command/control state information associated with the bus protocol over the first signal line and the second signal line by driving different respective combinations of static states on the first signal line and the second signal line, wherein each respective combination of driven static states represents information indicative of a different respective command/control state associated with the specified bus protocol.
18. The method of claim 17 , wherein said driving different respective combinations of static states on the first signal line and the second signal line comprises driving the first signal line and the second signal line to specific respective logic levels for specified respective time periods, wherein the respective specified time periods satisfy timing specifications set forth in the specified bus protocol.
19. A method comprising:
during a first mode of operation:
receiving data on a first signal line according to a specified bus protocol; and
receiving, source-synchronously with the data, a clock signal on a second signal line; and
during a second mode of operation:
instead of receiving the data and the clock signal, detecting over the first signal line and the second signal line command/control state information associated with the bus protocol, by detecting different respective combinations of static states on the first signal line and the second signal line, wherein each respective combination of driven static states represents information indicative of a different respective command/control state associated with the specified bus protocol.
20. The method of claim 17 , wherein said detecting the different respective combinations of static states on the first signal line and the second signal line comprises detecting respective logic levels on the first signal line and the second signal line for specified respective time periods, wherein the respective specified time periods satisfy timing specifications set forth in the specified bus protocol.
21. The method of claim 19 , further comprising:
during the first mode of operation:
sampling the received data on one or more of:
a rising edge of the received clock signal; or
a falling edge of the received clock signal.