Drive control signal generating circuit
View Patent ↗A drive control signal generating circuit that generates a drive control signal for driving a motor includes an output control circuit that includes a flip-flop in which a state changes by a rotational state signal of the motor crossing a reference value and generates a motor drive control signal according to the state of the flip-flop, a clock generating circuit that generates a clock that defines a time of reading data in the flip-flop of the output control circuit; and a PWM conversion circuit that PWM-converts the drive control signal using the clock as a PWM signal. The clock has a frequency in which the output control circuit operates and has a duty ratio of the PWM signal.
1. A drive control signal generating circuit that generates a drive control signal for driving a motor, the drive control signal generating circuit comprising:
an output control circuit that comprises a flip-flop in which a state changes by a rotational state signal of the motor crossing a reference value and generates a motor drive control signal according to the state of the flip-flop;
a clock generating circuit that generates a clock that defines a time of reading data in the flip-flop of the output control circuit; and
a PWM conversion circuit that PWM-converts the drive control signal using the clock as a PWM signal, wherein
the clock has a frequency in which the output control circuit operates and has a duty ratio of the PWM signal,
the clock generating circuit comprises:
a unit that generates a period of an H level of the clock by charging a first capacitor; and
a unit that generates a period of an L level of the clock by charging a second capacitor, and
the duty ratio of the clock is set by setting a capacitance ratio between the first and second capacitors.
2. The drive control signal generating circuit according to claim 1 , wherein
the output control circuit generates a drive control signal of a rectangular waveform with an electricity application period of less than 180°.
3. The drive control signal generating circuit according to claim 1 , wherein
the output control circuit generates a drive control signal of a rectangular waveform with an electricity application period of less than 180°.
4. The drive control signal generating circuit according to claim 1 , wherein
the output control circuit operates using one of a time of a rise or a time of a fall of the clock.