Bump with protection structure
A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.
1. A semiconductor device, comprising:
a semiconductor substrate;
a passivation layer over the semiconductor substrate;
a post-passivation interconnect (PPI) line overlying the passivation layer;
a protection structure overlying the passivation layer and the PPI line, wherein the protection structure has an opening at least exposing a portion of the PPI line; and
a bump structure formed in the protection structure and electrically connected to the PPI line through the opening of the protection structure;
wherein the protection structure comprises
a polymer layer having opposite top and bottom surfaces, and opposite sidewall surfaces connecting the top surface and the bottom surface, and
a dielectric layer surrounding the polymer layer, the dielectric layer covering the top surface, the bottom surface and the opposite sidewall surfaces of the polymer layer.
2. The semiconductor device of claim 1 , wherein the dielectric layer is formed of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, tetra-ethyl-ortho-silicate (TEOS) oxide, silicon oxide, or combinations thereof.
3. The semiconductor device of claim 1 , wherein one of the sidewall surfaces of the polymer layer faces the bump structure and is separated from the bump structure by the dielectric layer.
4. The semiconductor device of claim 1 , wherein one of the sidewall surfaces of the polymer layer faces the bump structure and is separated from the PPI line by the dielectric layer.
5. The semiconductor device of claim 1 , wherein the polymer layer has a thickness greater than 30 μm.
6. The semiconductor device of claim 1 , wherein the opening of the protection structure further exposes a portion of the passivation layer adjacent to the PPI line.
7. The semiconductor device of claim 1 , wherein the bump structure comprises an under-bump metallization (UBM) layer lining the opening of the protection structure.
8. The semiconductor device of claim 7 , wherein the UBM layer comprises an overhang portion on a top surface of the protection structure.
9. The semiconductor device of claim 7 , wherein the bump structure comprises a conductive bump formed on the UBM layer and filling the opening of the protection structure.
10. The semiconductor device of claim 9 , wherein the conductive bump protrudes from a top surface of the protection structure.
11. The semiconductor device of claim 6 , wherein the sidewall surface of the polymer layer is separated from the bump structure or from the PPI line by the dielectric layer.