LDMOS device structure and manufacturing method of the same
View Patent ↗The present invention discloses an LDMOS device structure, including a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell; each isolation region includes a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings; the height of the isolation region is smaller than that of a gate of the MOS transistor cell. The present invention also discloses a manufacturing method of the LDMOS device structure, including forming isolation trenches by lithography and etching processes, then forming isolation regions of SiO 2 by depleting silicon between isolation trenches through high-temperature drive-in. The present invention can reduce parasitic capacitance, surface unevenness and difficulty of subsequent process and realize the production of small-size gate devices by forming a thicker field oxide layer and a gap structure of isolation trenches.
1. An LDMOS device structure, comprising a MOS transistor cell, wherein an isolation region is formed on each outer side of both a source region and a drain region of the MOS transistor cell;
each isolation region formed of silicon dioxide comprises a plurality of isolation trenches and isolates the MOS transistor cell from its surroundings;
a height of the isolation region is shorter than or equal to that of a gate of the MOS transistor cell,
wherein air gaps exist in the isolation trenches.
2. The LDMOS device structure according to claim 1 , wherein the isolation trenches are deep trenches.
3. The LDMOS device defined by claim 1 further comprising:
(i) an isolation layer formed on a substrate,
(ii) a connecting layer formed on and connected to said substrate and said source in the isolation layer.
4. The LDMOS device defined by claim 3 , wherein the isolation trenches are deep trenches.