Integrated circuit having latch-up recovery circuit
View Patent ↗An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.
1. An integrated circuit comprising:
a first transistor having a first current electrode, a second current electrode, and a control electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode;
a switch for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal;
a voltage regulator having an input coupled to receive an externally generated power supply voltage, the voltage regulator having output terminal for providing the power supply voltage; and
a power-on reset circuit having a latch-up detection circuit coupled to receive the externally generated power supply voltage and to a control terminal of the switch, the latch-up detection circuit for detecting that the externally generated power supply voltage has dropped below a predetermined threshold voltage, and in response to detecting that the externally generated power supply voltage has dropped below the predetermined threshold voltage, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.
2. The integrated circuit of claim 1 , wherein the first transistor is characterized as being a P-channel transistor, and the second transistor is characterized as being an N-channel transistor.
3. The integrated circuit of claim 1 , wherein the first transistor and the second transistor are part of a logic circuit.
4. The integrated circuit of claim 1 , wherein the switch comprises a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a ground terminal, and a control electrode coupled to the power-on reset circuit.
5. The integrated circuit of claim 1 , wherein the switch comprises a third transistor having a first current electrode coupled to receive the power supply voltage, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode coupled to the power-on reset circuit.
6. An integrated circuit comprising:
a first transistor having a first current electrode, a second current electrode, and a control electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode;
a switch for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal, wherein the switch comprises a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to a ground terminal, and a control electrode coupled to the power-on reset circuit;
a power-on reset circuit having a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch, the latch-up detection circuit for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage; and
a fourth transistor having a first current electrode coupled to receive the power supply voltage, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode coupled to the power-on reset circuit.
7. An integrated circuit comprising:
a first transistor having a first current electrode, a second current electrode, and a control electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode;
a switch for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal;
a power-on reset circuit having a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch, the latch-up detection circuit for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage; and
a voltage regulator having an input coupled to receive an externally generated power supply voltage, the voltage regulator having output terminal for providing the power supply voltage.
8. The integrated circuit of claim 1 , wherein the first transistor and the second transistor are coupled together to form an inverter.
9. The integrated circuit of claim 1 , wherein the low voltage condition comprises the externally generated power supply voltage dropping below a predetermined threshold voltage.
10. An integrated circuit comprising:
a first power supply voltage terminal;
a second power supply voltage terminal;
a first P-channel transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode, and a control electrode;
a first N-channel transistor having a first current electrode coupled to the second current electrode of the first P-channel transistor, a second current electrode, and a control electrode;
a second N-channel transistor having a first current electrode coupled to the second current electrode of the first N-channel transistor, a second current electrode coupled to the second power supply voltage terminal, and a control electrode;
a first bias control circuit coupled to provide a first bias signal to the control electrode of the second N-channel transistor;
a latch-up detection circuit coupled to the first power supply voltage terminal for detecting when a power supply voltage provided to the first power supply voltage terminal drops below a predetermined threshold voltage; and
a power-on reset circuit coupled to the latch-up detection circuit and to an input terminal of the bias control circuit, the power-on reset circuit for causing the integrated circuit to initiate a power-on reset sequence and to cause the bias control circuit to make the second N-channel transistor substantially non-conductive.
11. The integrated circuit of claim 10 , further comprising a voltage regulator having an input terminal coupled to the first power supply voltage terminal, and an output terminal coupled to the first current electrode of the first P-channel transistor.
12. The integrated circuit of claim 10 , wherein the control electrodes of the first P-channel transistor and the first N-channel transistor are coupled together.
13. The integrated circuit of claim 10 , further comprising a second P-channel transistor having a first current electrode coupled to the first power supply voltage terminal, a second current electrode coupled to the first current electrode of the first P-channel transistor, and a control electrode.
14. The integrated circuit of claim 13 , further comprising a second bias control circuit coupled to provide a second bias signal to the control electrode of the second P-channel transistor, and an input terminal coupled to the power-on reset circuit.
15. The integrated circuit of claim 10 , wherein the integrated circuit is characterized as being a data processing system.
16. In an integrated circuit, a method for preventing latch-up in first and second transistors coupled in series, the method comprising:
receiving and regulating an externally generated power supply voltage to provide a power supply voltage;
supplying the first and second transistors with the power supply voltage;
monitoring the externally generated power supply voltage to detect a low voltage condition caused by the latch-up in the first and second transistors;
detecting that the externally generated power supply voltage has dropped below a predetermined threshold voltage;
initiating a power-on reset (POR) operation in the integrated circuit in response to detecting that the externally generated power supply voltage has dropped below the predetermined threshold voltage;
decoupling the first and second transistors from the power supply voltage for a predetermined time period as part of the POR operation; and
re-supplying the power supply voltage to the first and second transistors following the predetermined time period.
17. The method of claim 16 , wherein decoupling the first and second transistors from the power supply voltage further comprises turning off a first switch that is coupled between the first and second transistors and a first power supply voltage terminal.
18. In an integrated circuit, a method for preventing latch-up in first and second transistors coupled in series, the method comprising:
supplying the first and second transistors with a power supply voltage;
monitoring the power supply voltage to detect a low voltage condition caused by the latch-up in the first and second transistors;
detecting that the power supply voltage has dropped below a predetermined threshold voltage;
initiating a power-on reset (POR) operation in the integrated circuit in response to detecting that the power supply voltage has dropped below the predetermined threshold voltage;
decoupling the first and second transistors from the power supply voltage for a predetermined time period as part of the POR operation by turning off a first switch that is coupled between the first and second transistors and a first power supply voltage terminal, and turning off a second switch that is coupled between the first and second transistors and a second power supply voltage terminal; and
re-supplying the power supply voltage to the first and second transistors following the predetermined time period.
19. The method of claim 18 , wherein turning off the first switch further comprises removing a bias voltage from a control electrode of a transistor coupled between the first and second transistor and the first power supply voltage terminal.
20. The method of claim 18 , wherein supplying the first and second transistors with a power supply voltage further comprises supplying the first and second transistors with a regulated power supply voltage.