Digital logic controller for regulating voltage of a system on chip
View Patent ↗A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.
1. A digital logic controller for regulating a voltage of a system on chip, the digital logic controller comprising:
a first input for receiving a first signal, the first signal being a reference signal and having a first property that is at least substantially constant over a range of operating conditions of the system on chip;
a second input for receiving a second signal, the second signal having a second property that is indicative of an operating condition of the system on chip, the second property being variable over the range of operating conditions of the system on chip;
an output; and
a comparator for comparing the first property of the first signal and the second property of the second signal, wherein
based on the comparison, the digital logic controller outputs to a voltage regulator, via the output, a regulation signal for regulating the voltage of the system on chip at or near a target voltage a predetermined amount higher than a minimum operating voltage of the system on chip, wherein the predetermined amount includes a worst case voltage drop in the System on chip due to peak current consumption.
2. The digital logic controller of claim 1 , wherein the digital logic controller reduces the voltage of the system on chip, based on the comparison when the system on chip is operating in a condition that is better than a poorest-acceptable operating condition.
3. The digital logic controller of claim 2 , wherein the digital logic controller, based on the determination, reduces the voltage of the system on chip if the digital logic controller has not detected the voltage has been reduced to the target value.
4. The digital logic controller of claim 3 , wherein the digital logic controller reduces the voltage of the system on chip until the digital logic controller detects the voltage has been reduced to the target value.
5. The digital logic controller of claim 1 , wherein the digital logic controller increases the voltage of the system on chip in dependence of determining from the comparison that the system on chip is not operating in a condition that is better than a poorest-acceptable operating condition.
6. The digital logic controller of claim 1 , wherein:
the first signal is derived from a first clock signal of a crystal oscillator, and the first property is a first frequency of the first signal;
the second signal is derived from a second clock signal of a ring oscillator, and the second property is a second frequency of the second signal; and
the comparator compares the first frequency with the second frequency by determining which of a first count of transitions of the first signal and a second count of transitions of the second signal reaches a predetermined count first.
7. The digital logic controller of claim 6 , wherein the digital logic controller determines the first count has reached the predetermined count at a first count expiry time and outputs the regulation signal to regulate the voltage based on whether the second count has reached the predetermined count at the first count expiry time.
8. The digital logic controller of claim 7 , wherein the digital logic controller outputs the regulation signal to reduce the voltage of the system on chip if, at the first count expiry time, the second count has reached the predetermined count and the digital logic controller has not detected the voltage has been reduced to the target value.
9. The digital logic controller of claim 7 , wherein the digital logic controller outputs the regulation signal to increase the voltage of the system on chip if, at the first count expiry time, the second count has not reached the predetermined count.
10. The digital logic controller of claim 1 , further comprising a voltage regulation memory for storing a last value of the regulation signal at a time when regulation of the voltage of the system on chip is suspended, and wherein the digital logic controller, upon re-commencement of regulation of the voltage of the system on chip, retrieves the last value from the voltage regulation memory and sets the regulation signal to the last value.
11. A system on chip (SoC), comprising:
a first signal generator for generating a first signal, the first signal being a reference signal and having a first property that is at least substantially constant over a range of operating conditions of the system on chip;
a second signal generator for generating a second signal having a second property that is indicative of an operating condition of the system on chip, the second property being variable over the range of operating conditions of the system on chip;
a voltage regulator; and
a digital logic controller comprising:
a first input for receiving the first signal;
a second input for receiving the second signal;
an output; and
a comparator for comparing the first property of the first signal and the second property of the second signal, wherein
based on the comparison, the digital logic controller outputs to the voltage regulator, via the output, a regulation signal for regulating the voltage of the system on chip at or near a target voltage that is a predetermined amount higher than a minimum operating voltage of the system on chip, wherein the predetermined amount includes a worst case voltage drop in the SoC due to peak current consumption.
12. The system on chip of claim 11 , wherein the digital logic controller is configured to reduce the voltage of the system on chip in dependence of determining from the comparison that the system on chip is operating in a condition which is better than a poorest-acceptable operating condition.
13. The system on chip of claim 12 , wherein the digital logic controller is configured, from the determination, to reduce the voltage of the system on chip if the digital logic controller has not detected the voltage has been reduced to the target value.
14. The system on chip of claim 13 , wherein the digital logic controller is configured to reduce the voltage of the system on chip until detecting the voltage has been reduced to the target value.
15. The system on chip of claim 11 , wherein the digital logic controller is configured to increase the voltage of the system on chip in dependence of determining from the comparison that the system on chip is not operating in a condition which is better than a poorest-acceptable operating condition.
16. The system on chip of claim 11 , wherein:
the first signal is derived from a first clock signal of a crystal oscillator, and the first property is a first frequency of the first signal;
the second signal is derived from a second clock signal of a ring oscillator, and the second property is a second frequency of the second signal; and
the comparator is configured to compare the first frequency with the second frequency by determining which of a first count of transitions of the first signal and a second count of transitions of the second signal reaches a predetermined count first.
17. The system on chip of claim 16 , wherein the digital logic controller is configured to determine the first count has reached the predetermined count at a first count expiry time and to output the regulation signal to regulate the voltage in dependence of whether the second count has reached the predetermined count at the first count expiry time.
18. The system on chip of claim 17 , wherein the digital logic controller is configured to output the regulation signal to reduce the voltage of the system on chip if, at the first count expiry time, the second count has reached the predetermined count and the digital logic controller has not detected the voltage has been reduced to the target value.
19. The system on chip of claim 11 , further comprising a voltage regulation memory for storing a last value of the regulation signal at a time when regulation of the voltage of the system on chip is suspended, the digital logic controller being configured, upon re-commencement of regulation of the voltage of the system on chip, to retrieve the last value from the voltage regulation memory and to set the regulation signal to the last value.
20. A method for regulating a voltage of a system on chip, the method comprising:
providing a digital logic controller comprising:
a first input;
a second input;
an output; and
a comparator;
receiving, at the first input of the digital logic controller, a first signal generated by a first signal generator, the first signal being a reference signal and having a first property which is at least substantially constant over a range of operating conditions of the system on chip;
receiving, at the second input of the digital logic controller, a second signal generated by a second signal generator, the second signal having a second property which is indicative of an operating condition of the system on chip, the second property being variable over the range of operating conditions of the system on chip;
comparing, using the comparator, the first property of the first signal and the second property of the second signal; and in dependence of the comparison, regulating the voltage of the system on chip at or near a target voltage a predetermined amount higher than a minimum operating voltage of the system on chip by outputting, via the output of the digital logic controller, a regulation signal to a voltage regulator, wherein the predetermined amount includes a worst case voltage drop in the system on chip due to peak current consumption.