Buck-boost converter using timers for mode transition control
View Patent ↗A DC-to-DC, buck-boost voltage converter includes a duty cycle controller configured to generate control signals for a buck driver configured to drive first and second buck switching transistors at a buck duty cycle and to generate control signals for a boost driver configured to drive first and second boost switching transistors at a boost duty cycle. The duty cycle controller includes at least a duty cycle timer and an offset timer where the duty cycle controller applies the duty cycle timer and the offset timer to control transitions between the buck, the buck-boost and the boost operation modes of the voltage converter.
1. A DC-to-DC, buck-boost voltage converter, the converter comprising a first buck switching transistor coupled between an input voltage and a first terminal of an inductor, a second buck switching transistor coupled between the first terminal of the inductor and ground, a first boost switching transistor coupled between a second terminal of the inductor and ground, and a second boost switching transistor coupled between the second terminal of the inductor and an output terminal of the converter, the converter comprising:
a duty cycle controller configured to generate control signals for a buck driver configured to drive the first and second buck switching transistors at a buck duty cycle and to generate control signals for a boost driver configured to drive the first and second boost switching transistors at a boost duty cycle, the duty cycle controller comprising at least a duty cycle timer value and an offset timer value, wherein the duty cycle controller uses the duty cycle timer value and the offset timer value to establish one or more transition thresholds to control transitions between the buck, the buck-boost and the boost operation modes of the voltage converter,
wherein the duty cycle timer value is indicative of a minimum on time or a minimum off time of the buck and boost switching transistors, and the offset timer value is indicative of variations and tolerance in the transistor switch time over temperature and process variations; and
wherein the duty cycle controller is configured to measure the buck duty cycle and the boost duty cycle, and to digitally compare the buck duty cycle and the boost duty cycle to the one or more transition thresholds to control the transitions between the buck, the buck-boost and the boost operation modes of the voltage converter.
2. The buck-boost voltage converter of claim 1 , wherein the duty cycle controller further comprises a hysteresis threshold being N times the offset timer value, N being a positive number.
3. The buck-boost voltage converter of claim 1 , wherein the duty cycle controller comprises a phase-locked loop (PLL) to generate the duty cycle timer value and the offset timer value as harmonics of the PLL.
4. The buck-boost voltage converter of claim 1 , wherein when entering into the buck-boost mode from the buck mode, the duty cycle controller reduces the duty cycle of the first buck switching transistor to increase an on-time of the second buck switching transistor to compensate for the first boost switching transistor having a minimum on- time at a start of the buck-boost mode of operation.
5. The buck-boost voltage converter of claim 1 , wherein when entering into the boost mode from the buck-boost mode, the duty cycle controller decreases the duty cycle of the first boost switching transistor to compensate for the first buck switching transistor stopping switching at a start of the boost mode of operation, where the first buck switching transistor has a minimum on-time prior to the converter entering the boost mode.
6. The buck-boost voltage converter of claim 1 , wherein the duty cycle controller uses the duty cycle timer value and the offset timer value to establish a first transition threshold for transitioning from the buck mode to the buck-boost mode, a second transition threshold for transitioning from the buck-boost mode to the buck mode, and a third transition threshold for transitioning from the buck-boost mode to the boost mode.
7. The buck-boost voltage converter of claim 6 , wherein the first transition threshold comprises the maximum buck duty cycle reaching 1−(D timer*f s ), where D-timer is the duty cycle timer value and f s denotes the switching frequency of the voltage converter.
8. The buck-boost voltage converter of claim 6 , wherein the second transition threshold comprises the maximum buck duty cycle decreasing below 1−(D-timer+2*O-timer)*f s ), where D-timer is the duty cycle timer value, the O-timer is the offset timer value and f s denotes the switching frequency of the voltage converter.
9. The buck-boost voltage converter of claim 6 , wherein the third transition threshold comprises the sum of the buck duty cycle and the boost duty cycle reaching 1+((2*O-timer)f s ), where D-timer is the duty cycle timer value, the O-timer is the offset timer value and f s denotes the switching frequency of the voltage converter.
10. The buck-boost voltage converter of claim 6 , wherein the duty cycle controller digitally compares the buck duty cycle and the boost duty cycle to the first, second and third transition thresholds to control the transitions between the buck, the buck-boost and the boost operation modes of the voltage converter.
11. The buck-boost voltage converter of claim 1 , wherein the duty cycle controller comprises one or more ring oscillators to generate the duty cycle timer value and the offset timer value.
12. The buck-boost voltage converter of claim 11 , wherein the one or more ring oscillators has a frequency higher than a switching frequency of the voltage converter.
13. The buck-boost voltage converter of claim 11 , wherein the one or more ring oscillators has a frequency being synchronous to a switching frequency of the voltage converter.
14. The buck-boost voltage converter of claim 11 , wherein the one or more ring oscillators has a frequency being asynchronous to a switching frequency of the voltage converter.