METHOD OF MAKING A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE
Forming an NVM structure includes forming a floating gate layer; forming a first dielectric layer over the floating gate layer; forming a plurality of nanocrystals over the first dielectric layer; etching the first dielectric layer using the plurality of nanocrystals as a mask to form dielectric structures, wherein the floating gate layer is exposed between adjacent dielectric structures; etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures, wherein the first depth is less than a thickness of the floating gate layer; patterning the floating gate layer to form a floating gate; forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the patterned structures and on the floating gate layer between adjacent patterned structures; and forming a control gate layer over the second dielectric layer.
1 . A method for forming a non-volatile memory (NVM) structure, the method comprising:
forming a gate dielectric over a semiconductor substrate;
forming a floating gate layer over the gate dielectric;
forming a first dielectric layer over the floating gate layer;
forming a plurality of nanocrystals over the first dielectric layer;
etching the first dielectric layer using the plurality of nanocrystals as a mask to form a plurality of dielectric structures of the first dielectric layer, wherein the floating gate layer is exposed between adjacent dielectric structures of the plurality of dielectric structures;
etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures of the floating gate layer, wherein the first depth is less than a thickness of the floating gate layer;
removing the plurality of nanocrystals in situ relative to the etching the first depth into the floating gate layer;
removing the plurality of dielectric structures;
patterning the floating gate layer to form a floating gate, wherein the floating gate comprises a set of patterned structures of the plurality of patterned structures;
forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the set of patterned structures and on the floating gate layer between adjacent patterned structures of the set of patterned structures; and
forming a control gate layer over the second dielectric layer, wherein the control gate layer is formed between adjacent patterned structures of the set of patterned structures.
2 . The method of claim 1 , wherein the step of forming the plurality of nanocrystals over the first dielectric layer is performed such that each nanocrystal of the plurality of nanocrystals has a diameter of less than 100 Angstroms.
3 . The method of claim 1 , wherein the step of forming the plurality of nanocrystals over the first dielectric layer is performed such that each nanocrystal of the plurality of nanocrystals has an average diameter of about 50 Angstroms.
4 . The method of claim 1 , wherein the step of forming the plurality of nanocrystals over the first dielectric layer is performed such that a distance between adjacent nanocrystals of the plurality of nanocrystals is about 400 Angstroms.
5 . The method of claim 1 , wherein the step of etching into the floating gate layer using the plurality of dielectric structures as a mask is performed such that a distance between adjacent patterned structures of the plurality of patterned structures is about 400 Angstroms.
6 . The method of claim 1 , wherein the step of forming the plurality of nanocrystals is further characterized in that each of the nanocrystals of the plurality of nanocrystals comprises silicon.
7 . The method of claim 1 , wherein the step of forming a first dielectric layer over the floating gate layer is further characterized in that the first dielectric layer comprises oxide.
8 . The method of claim 1 , wherein the step of forming the second dielectric layer comprises:
forming a first oxide layer over the floating gate, wherein the first oxide layer is formed over the set of patterned structures and on the floating gate layer between adjacent patterned structures of the set of patterned structures;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
9 . The method of claim 1 , wherein the step of forming the floating gate layer is further characterized in that the floating gate layer comprises polysilicon.
10 . The method of claim 1 , wherein the step of forming the control gate layer is further characterized in that the control gate layer comprises a material selected from a group consisting of polysilicon and metal.
11 . The method of claim 1 , wherein prior to the step of patterning the floating gate layer, the method further comprises performing an anneal in an ambient containing hydrogen.
12 . The method of claim 1 , wherein the step of etching the first depth into the floating gate layer is further characterized in that the first depth is at least half of the thickness of the floating gate layer.
13 . A method for forming a non-volatile memory (NVM) structure, the method comprising:
forming a gate dielectric over a semiconductor substrate;
forming a floating gate layer over the gate dielectric;
forming a first dielectric layer over the floating gate layer;
forming a plurality of nanocrystals over the first dielectric layer, wherein each nanocrystals of the plurality of nanocrystals has diameter of about 50 Angstroms and a distance between adjacent nanocrystals of the plurality of nanocrystals is at least 300 Angstroms;
etching the first dielectric layer using the plurality of nanocrystals as a mask to form a plurality of dielectric structures of the first dielectric layer, wherein the floating gate layer is exposed between adjacent dielectric structures of the plurality of dielectric structures;
etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures of the floating gate layer, wherein the first depth is less than a thickness of the floating gate layer;
removing the plurality of nanocrystals in situ with the etching the first depth of the plurality of dielectric structures;
removing the plurality of dielectric structures;
patterning the floating gate layer to form a floating gate, wherein the floating gate comprises a set of patterned structures of the plurality of patterned structures;
forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the set of patterned structures and on the floating gate layer between adjacent patterned structures of the set of patterned structures; and
forming a control gate layer over the second dielectric layer, wherein the control gate layer is formed between adjacent patterned structures of the set of patterned structures.
14 . The method of claim 13 , wherein the step of forming the plurality of nanocrystals over the first dielectric layer is performed such that a distance between adjacent nanocrystals of the plurality of nanocrystals is about 400 Angstroms.
15 . The method of claim 14 , wherein the step of forming the plurality of nanocrystals over the first dielectric layer is performed such that each nanocrystal of the plurality of nanocrystals has a diameter of at most 50 Angstroms.
16 . The method of claim 13 , wherein the step of forming the plurality of nanocrystals is further characterized in that each of the nanocrystals of the plurality of nanocrystals comprises silicon.
17 . The method of claim 13 , wherein the step of forming a first dielectric layer over the floating gate layer is further characterized in that the first dielectric layer comprises oxide.
18 . The method of claim 13 , wherein the step of forming the second dielectric layer comprises:
forming a first oxide layer over the floating gate, wherein the first oxide layer is formed over the set of patterned structures and on the floating gate layer between adjacent patterned structures of the set of patterned structures;
forming a nitride layer on the first oxide layer; and
forming a second oxide layer on the nitride layer.
19 . The method of claim 13 , wherein the step of forming the floating gate layer is further characterized in that the floating gate layer comprises polysilicon, and the step of forming the control gate layer is further characterized in that the control gate layer comprises polysilicon.
20 . A method for forming a non-volatile memory (NVM) structure, the method comprising:
forming a gate dielectric over a semiconductor substrate;
forming a floating gate layer over the gate dielectric;
forming an oxide layer over the floating gate layer;
forming a plurality of silicon nanocrystals over the oxide layer, wherein each silicon nanocrystals of the plurality of silicon nanocrystals has a diameter of about 50 Angstroms and a distance between adjacent silicon nanocrystals of the plurality of silicon nanocrystals is at least 300 Angstroms;
etching the oxide layer using the plurality of silicon nanocrystals as a mask to form a plurality of oxide structures of the oxide layer, wherein the floating gate layer is exposed between adjacent oxide structures of the plurality of oxide structures;
etching a first depth into the floating gate layer using the plurality of oxide structures as a mask to form a plurality of patterned structures of the floating gate layer, wherein the first depth is at least half of a thickness of the floating gate layer and less than an entire thickness of the floating gate layer;
removing the plurality of silicon nanocrystals in situ relative to the etching the first depth into the floating gate layer;
removing the plurality of oxide structures;
patterning the floating gate layer to form a floating gate, wherein the floating gate comprises a set of patterned structures of the plurality of patterned structures;
forming an oxide-nitride-oxide layer over the floating gate, wherein the oxide-nitride-oxide layer is formed over the set of patterned structures and on the floating gate layer between adjacent patterned structures of the set of patterned structures; and
forming a control gate layer over the oxide-nitride-oxide layer, wherein the control gate layer is formed between adjacent patterned structures of the set of patterned structures.