Solid state drive architecture
View Patent ↗Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
1. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory; and
a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information, the flash fabric header information including a write cancel operation bit that directs the flash scheduler to cancel a write of the data packet to an array of flash memory using a bypass queue;
wherein the scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
2. The solid state drive of claim 1 , further comprising the flash scheduler extracting priority information of each data packet from the flash fabric header information of the data packet, and wherein the flash scheduler schedules high priority data packets before low priority packets, enabling data packet movement through the non-blocking fabric.
3. The solid state drive of claim 2 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory.
4. The solid state drive of claim 2 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory, and at least one of receiving and providing data packets to at least one of an embedded central processing unit (eCPU) and volatile memory.
5. The solid state drive of claim 2 , further comprising the priority information of each of the data packet being influenced by events external to the flash scheduler.
6. The solid state drive of claim 1 , wherein if a scheduled data packet fails, then the flash scheduler provides an indication of the failure to an eCPU connected to at least one port of the non-blocking fabric.
7. The solid state drive of claim 1 , wherein at least one port of the non-blocking fabric comprises at least one electrical connection to at least an embedded central processing unit (eCPU).
8. The solid state drive of claim 1 , wherein the flash fabric header information comprises a write immediate operation bit that directs the flash scheduler to increase the priority of the data packet.
9. The solid state drive of claim 1 , wherein the flash fabric header information comprises a multiple queues operation bit that directs the flash scheduler to put the data packet in multiple queues.
10. The solid state drive of claim 1 , wherein the flash fabric header information comprises a no retries operation bit that directs the flash scheduler to avoid retries of operations of the data packet.
11. The solid state drive of claim 1 , wherein the flash fabric header information comprises stacked header information, wherein the flash schedule performs multiple operations based on the stacked header information, autonomous from an embedded central processing unit (eCPU) connected to the first port of the non-blocking fabric.
12. The solid state drive of claim 1 , further comprising a data scrambler.
13. The solid state drive of claim 1 , further comprising a data pattern compression engine, wherein the data pattern compression engine parses data packets, recognizing patterns and compresses the data packets based on the recognized patterns.
14. The solid state drive of claim 1 , further comprising a circular buffer for tracking alerts and errors of operation of the flash scheduler.
15. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises at least a first port and a second port, wherein the second port comprises a plurality of Input/Outputs (I/Os) that are each connected to a non-volatile memory controller; and
a flash scheduler for scheduling data traffic through the non-block fabric, wherein the data traffic comprises a plurality of data packets, and wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information, the flash fabric header information including a write cancel operation bit that directs the flash scheduler to cancel a write of the data packet to an array of flash memory using a bypass queue.
16. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises at least a first port and a second port, wherein the second port comprises a plurality of Input/Outputs (I/Os) that are each connected to a non-volatile memory controller; and
a flash scheduler for scheduling data traffic through the non-block fabric, wherein the data traffic comprises a plurality of data packets, and wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information, the flash fabric header information including a multiple queues operation bit that directs the flash scheduler to put the data packet in multiple queues.
17. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises at least a first port and a second port, wherein the second port comprises a plurality of Input/Outputs (I/Os) that are each connected to a non-volatile memory controller; and
a flash scheduler for scheduling data traffic through the non-block fabric, wherein the data traffic comprises a plurality of data packets, and wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information; and retries operation bit that directs the flash scheduler to avoid retries of operations of the data packet.
18. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises at least a first port and a second port, wherein the second port comprises a plurality of Input/Outputs (I/Os) that are each connected to a non-volatile memory controller;
a flash scheduler for scheduling data traffic through the non-block fabric, wherein the data traffic comprises a plurality of data packets, and wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information, the flash fabric header information including; and
a data pattern compression engine, wherein the data pattern compression engine parses data packets, recognizing patterns and compresses the data packets based on the recognized patterns.
19. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory; and
a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information, the flash fabric header information including a multiple queues operation bit that directs the flash scheduler to put the data packet in multiple queues;
wherein the scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
20. The solid state drive of claim 19 , further comprising the flash scheduler extracting priority information of each data packet from the flash fabric header information of the data packet, and wherein the flash scheduler schedules high priority data packets before low priority packets, enabling data packet movement through the non-blocking fabric.
21. The solid state drive of claim 20 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory.
22. The solid state drive of claim 20 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory, and at least one of receiving and providing data packets to at least one of an embedded central processing unit (eCPU) and volatile memory.
23. The solid state drive of claim 20 , further comprising the priority information of each of the data packet being influenced by events external to the flash scheduler.
24. The solid state drive of claim 19 , wherein if a scheduled data packet fails, then the flash scheduler provides an indication of the failure to an eCPU connected to at least one port of the non-blocking fabric.
25. The solid state drive of claim 19 , wherein at least one port of the non-blocking fabric comprises at least one electrical connection to at least an embedded central processing unit (eCPU).
26. The solid state drive of claim 19 , wherein, the flash fabric header information comprises a write cancel operation bit that directs the flash scheduler to cancel a write of the data packet to an array of flash memory, and using a bypass queue.
27. The solid state drive of claim 19 , wherein the flash fabric header information comprises a write immediate operation bit that directs the flash scheduler to increase the priority of the data packet.
28. The solid state drive of claim 19 , wherein the flash fabric header information comprises a no retries operation bit that directs the flash scheduler to avoid retries of operations of the data packet.
29. The solid state drive of claim 19 , wherein the flash fabric header information comprises stacked header information, wherein the flash schedule performs multiple operations based on the stacked header information, autonomous from an embedded central processing unit (eCPU) connected to the first port of the non-blocking fabric.
30. The solid state drive of claim 19 , further comprising a data scrambler.
31. The solid state drive of claim 19 , further comprising a data pattern compression engine, wherein the data pattern compression engine parses data packets, recognizing patterns and compresses the data packets based on the recognized patterns.
32. The solid state drive of claim 19 , further comprising a circular buffer for tracking alerts and errors of operation of the flash scheduler.
33. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory; and
a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information, the flash fabric header information including a no retries operation bit that directs the flash scheduler to avoid retries of operations of the data packet,
wherein the scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
34. The solid state drive of claim 33 , further comprising the flash scheduler extracting priority information of each data packet from the flash fabric header information of the data packet, and wherein the flash scheduler schedules high priority data packets before low priority packets, enabling data packet movement through the non-blocking fabric.
35. The solid state drive of claim 34 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory.
36. The solid state drive of claim 34 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory, and at least one of receiving and providing data packets to at least one of an embedded central processing unit (eCPU) and volatile memory.
37. The solid state drive of claim 34 , further comprising the priority information of each of the data packet being influenced by events external to the flash scheduler.
38. The solid state drive of claim 33 , wherein if a scheduled data packet fails, then the flash scheduler provides an indication of the failure to an eCPU connected to at least one port of the non-blocking fabric.
39. The solid state drive of claim 33 , wherein at least one port of the non-blocking fabric comprises at least one electrical connection to at least an embedded central processing unit (eCPU).
40. The solid state drive of claim 33 , wherein the flash fabric header information including a write cancel operation bit that directs the flash scheduler to cancel a write of the data packet to an array of flash memory, and using a bypass queue.
41. The solid state drive of claim 33 , wherein the flash fabric header information comprises a write immediate operation bit that directs the flash scheduler to increase the priority of the data packet.
42. The solid state drive of claim 33 , wherein the flash fabric header information comprises a multiple queues operation bit that directs the flash scheduler to put the data packet in multiple queues.
43. The solid state drive of claim 33 , wherein the flash fabric header information comprises stacked header information, wherein the flash schedule performs multiple operations based on the stacked header information, autonomous from an embedded central processing unit (eCPU) connected to the first port of the non-blocking fabric.
44. The solid state drive of claim 33 , further comprising a data scrambler.
45. The solid state drive of claim 33 , further comprising a data pattern compression engine, wherein the data pattern compression engine parses data packets, recognizing patterns and compresses the data packets based on the recognized patterns.
46. The solid state drive of claim 33 , further comprising a circular buffer for tracking alerts and errors of operation of the flash scheduler.
47. A solid state drive, comprising:
a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory;
a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information; and
a data pattern compression engine operable to parse data packets, recognize patterns and compress the data packets based on the recognized patterns; and
wherein the scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.
48. The solid state drive of claim 47 , further comprising the flash scheduler extracting priority information of each data packet from the flash fabric header information of the data packet, and wherein the flash scheduler schedules high priority data packets before low priority packets, enabling data packet movement through the non-blocking fabric.
49. The solid state drive of claim 48 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory.
50. The solid state drive of claim 48 , wherein the enabled data packet movement comprises at least one of reading and writing data packets from or to arrays of flash memory, and at least one of receiving and providing data packets to at least one of an embedded central processing unit (eCPU) and volatile memory.
51. The solid state drive of claim 48 , further comprising the priority information of each of the data packet being influenced by events external to the flash scheduler.
52. The solid state drive of claim 47 , wherein if a scheduled data packet fails, then the flash scheduler provides an indication of the failure to an eCPU connected to at least one port of the non-blocking fabric.
53. The solid state drive of claim 47 , wherein at least one port of the non-blocking fabric comprises at least one electrical connection to at least an embedded central processing unit (eCPU).
54. The solid state drive of claim 47 , wherein the flash fabric header information including a write cancel operation bit that directs the flash scheduler to cancel a write of the data packet to an array of flash memory, and using a bypass queue.
55. The solid state drive of claim 47 , wherein the flash fabric header information comprises a write immediate operation bit that directs the flash scheduler to increase the priority of the data packet.
56. The solid state drive of claim 47 , wherein the flash fabric header information comprises a multiple queues operation bit that directs the flash scheduler to put the data packet in multiple queues.
57. The solid state drive of claim 47 , wherein the flash fabric header information comprises a no retries operation bit that directs the flash scheduler to avoid retries of operations of the data packet.
58. The solid state drive of claim 47 , wherein the flash fabric header information comprises stacked header information, wherein the flash schedule performs multiple operations based on the stacked header information, autonomous from an embedded central processing unit (eCPU) connected to the first port of the non-blocking fabric.
59. The solid state drive of claim 47 , further comprising a data scrambler.
60. The solid state drive of claim 47 , further comprising a circular buffer for tracking alerts and errors of operation of the flash scheduler.