Package-on-package with fan-out WLCSP
A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.
1. A package-on-package, comprising:
a package carrier;
a semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face;
a rewiring laminate structure between the semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge;
a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and
an IC package mounted on the package carrier, wherein the IC package and the semiconductor die are at least partially overlapped.
2. The package-on-package according to claim 1 wherein the IC package is not in direct contact with the semiconductor die.
3. The package-on-package according to claim 1 further comprising an underfill between the rewiring laminate structure and the package carrier.
4. The package-on-package according to claim 1 further comprising a molding compound that encapsulates the semiconductor die and fills into a gap between the rewiring laminate structure and the chip side of the package carrier.
5. The package-on-package according to claim 1 wherein the re-routed metal layer redistributes the contact pads on the die face of the first semiconductor die to form fan-out bond pads, and the plurality of bumps are arranged on the fan-out bond pads respectively.
6. The package-on-package according to claim 1 further comprising a mold cap encapsulating at least a portion of the semiconductor die.
7. The package-on-package according to claim 1 wherein the semiconductor die is a baseband chip or an SoC chip, and the IC package is a DRAM chip, a flash memory chip or an RF chip.
8. The package-on-package according to claim 1 wherein the package carrier is a leadframe or a substrate comprising two metal wiring layers disposed on a chip side and on an opposite side respectively.
9. The package-on-package according to claim 1 wherein the rewiring laminate structure comprises an insulating layer, a re-routed metal layer and a solder resist layer.
10. A system-in-package, comprising:
a package carrier having a chip side and an opposite side;
a fan-out wafer level device comprising a semiconductor die, the fan-out wafer level device being mounted on the chip side of the package carrier;
an underfill between the package carrier and the fan-out wafer level device; and
an IC package mounted on the chip side of the package carrier, wherein the IC package and the fan-out wafer level device are at least partially overlapped.
11. The system-in-package according to claim 10 wherein the IC package is not in direct contact with the semiconductor die.
12. The system-in-package according to claim 10 wherein the semiconductor die is a baseband chip or an SoC chip, and the IC package is a DRAM chip, a flash memory chip or an RF chip.
13. The system-in-package according to claim 10 wherein the package carrier is a leadframe or a substrate comprising two metal wiring layers disposed on the chip side and on the opposite side respectively.
14. The system-in-package according to claim 10 wherein the fan-out wafer level device comprises a rewiring laminate structure comprising an insulating layer, a re-routed metal layer and a solder resist layer.
15. A system-in-package, comprising:
a package carrier having a chip side and an opposite side;
a fan-out wafer level device comprising a first semiconductor die, the fan-out wafer level device being mounted on the chip side of the package carrier;
a second semiconductor die mounted on the chip side of the package carrier, wherein the second semiconductor die and the fan-out wafer level device are at least partially overlapped; and
a molding compound encapsulating the fan-out wafer level device, wherein the molding compound fills into a gap between the package carrier and the fan-out wafer level device.
16. The system-in-package according to claim 15 wherein the second semiconductor die is not in direct contact with the fan-out wafer level device.
17. The system-in-package according to claim 15 wherein the first semiconductor die is a baseband chip or an SoC chip, and the second semiconductor die is a DRAM chip, a flash memory chip or an RF chip.
18. The system-in-package according to claim 15 wherein the package carrier is a leadframe or a substrate comprising two metal wiring layers disposed on the chip side and on the opposite side respectively.
19. The system-in-package according to claim 15 wherein the fan-out wafer level device comprises a rewiring laminate structure comprising an insulating layer, a re-routed metal layer and a solder resist layer.
20. A package-on-package, comprising:
a package carrier;
a first semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face;
a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge;
a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier; and
a second semiconductor die mounted on the package carrier, wherein the second semiconductor die and the first semiconductor die are at least partially overlapped.
21. The package-on-package according to claim 20 wherein the second semiconductor die is not in direct contact with the first semiconductor die.
22. The package-on-package according to claim 20 wherein the first semiconductor die comprises a baseband chip or an SoC chip, and the second semiconductor die comprises a DRAM chip, a flash memory chip or an RF chip.
23. The package-on-package according to claim 20 wherein the package carrier is a leadframe or a substrate comprising two metal wiring layers disposed on a chip side and on an opposite side respectively.
24. The package-on-package according to claim 20 wherein the rewiring laminate structure comprises an insulating layer, a re-routed metal layer and a solder resist layer.